Solid state image sensing device and method for subsampling using inter-column analog domain signal summation

• US 7,646,410 B2
• Filed: 03/08/2006
• Issued: 01/12/2010
• Est. Priority Date: 03/09/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Su-Hun
• Primary Examiner(s): Ho; Tuan
• Assistant Examiner(s): Lam; Hung H
• Application Number:
  US11/370,634
• Publication Number:
  US 20060203110A1
• Time in Patent Office: 1,406 Days
• Field of Search: 348/314, 348/324
• US Class Current: 348/241
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

Provided are a solid state image sensing device and method for sub-sampling using inter-column analog domain signal summation, where, in the solid state image sensing device, a CDS unit receives reset signals from neighboring columns of the same color in an APS array, receives video signals from pixels generating the reset signals, and generates modulation signals respectively corresponding to the differences between the reset signals and the video signals, the modulation signals are activated according to activation of the previous modulation signals, and a digital signal output circuit generates a corresponding digital signal based on the final modulation signal corresponding to the sum of inter-column analog video signals among the modulation signals.

Claims

1. A solid-state image sensing device comprising:

an Active Pixel Sensor (APS) array in which pixels are arranged in a two-dimensional matrix form, the APS array generating reset signals and video signals of respective columns in a selected row;

a Correlated Double Sampling (CDS) unit receiving reset signals from neighboring columns of the same color, receiving video signals from pixels generating the reset signals, and generating modulation signals respectively corresponding to the differences between the reset signals and the video signals such that each of the modulation signals is activated according to activation of the previous modulation signal; and

a digital signal output circuit generating a corresponding digital signal based on the instant of time when the logic state of the finally activated modulation signal among the modulation signals is changed,

wherein the CDS unit generates a modulation signal of a column, which is activated when the difference between the reset signal and the video signal from the column reaches a reference level in response to a ramp signal, and generates a modulation signal of the next column having the same color as that of the column, which is activated when the difference of the reset signal and the video signal of the next column reaches the reference level in response to the ramp signal according to activation of the previously generated modulation signal.

2. The solid state image sensing device of claim 1, wherein the instant of time when the logic state of the finally activated modulation signal is changed corresponds to the sum of the differences between the reset signals and the video signals of the same color.

3. The solid state image sensing device of claim 1, wherein the CDS unit generates modulation signal groups respectively corresponding to neighboring rows as many as the number of the reset signals or the video signals and sums up the pulse widths of finally activated modulation signals among the modulation signal groups, and the digital signal output circuit generates the corresponding digital signal based on the sum value, the neighboring rows having the same pattern as that of the selected row.

4. The solid state image sensing device of claim 1, wherein the digital signal output circuit sums up digital signals generated from the finally activated modulation signals among the modulation signal groups corresponding to the neighboring rows as many as the number of the reset signals or the video signals.

5. The solid-state image sensing device of claim 1, wherein the solid-state image sensing device is of a CIS type.

6. The solid state image sensing device of claim 1, wherein the APS array has a Bayer pattern pixel structure.

7. The solid state image sensing device of claim 1, wherein the CDS unit comprises:

a first switch transferring the ramp signal;

a second switch transferring the reset signals and the video signals; and

CDS circuits generating the differences between the reset signals and the video signals and generating the modulation signals activated when the differences reach the reference level in response to the ramp signal, respectively, the CDS circuits being included in the respective columns, the second switch being tuned off when the modulation signal generated in the previous column is activated.

8. The solid state image sensing device of claim 7, wherein each of the CDS circuits comprises:

a first capacitor connected between the output terminal of the second switch and a first node;

a second capacitor connected between the output terminal of the second switch and the output terminal of the first switch;

an amplifier comparing the signal of the first node with the reference level and amplifying the compared result; and

a third switch connected between the first node and the output terminal of the amplifier, a corresponding reset signal being transmitted to the first capacitor when the third switch is turned on, a corresponding video signal being transmitted to the first capacitor when the third switch is turned off.

9. A method for driving a solid state image sensing device comprising:

generating reset signals and video signals of respective columns in a selected row in an APS array in which pixels are arranged in a two-dimensional matrix form;

receiving reset signals from neighboring columns of the same color;

receiving video signals from pixels generating the reset signals;

generating modulation signals respectively corresponding to the differences between the reset signals and the video signals such that each of the modulation signals is activated according to activation of the previous modulation signal; and

generating a corresponding digital signal based on the instant of time when the logic state of the finally activated modulation signal among the modulation signals is changed,

wherein the generating the modulation signals comprises;

generating a modulation signal of a column, which is activated when the difference between the reset signal and the video signal from the column reaches a reference level in response to a ramp signal; and

generating a modulation signal of the next column having the same color as that of the column, which is activated when the difference of the reset signal and the video signal of the next column reaches the reference level in response to the ramp signal according to activation of the previously generated modulation signal.

10. The method of claim 9, wherein the instant of time when the logic state of the finally activated modulation signal is changed corresponds to the sum of the differences between the reset signals and the video signals of the same color.

11. The method of claim 9, further comprising:

generating modulation signal groups respectively corresponding to neighboring rows as many as the number of the reset signals or the video signals, the neighboring rows having the same pattern as that of the selected row;

summing up the pulse widths of finally activated modulation signals in the modulation signal groups; and

generating the corresponding digital signal based on the sum value.

12. The method of claim 9, further comprising summing up digital signals generated from the finally activated modulation signals in the modulation signal groups corresponding to the neighboring rows as many as the number of the reset signals or the video signals.

13. The method of claim 9, wherein the solid state image sensing device is of a CIS type.

14. The method of claim 10, wherein the APS array has a Bayer pattern pixel structure.

15. An image sensing device comprising:

active pixel sensing means having pixels disposed in a two-dimensional matrix for generating reset signals and video signals of respective columns in a selected row;

correlated double sampling means in signal communication with the active pixel sensing means for receiving the reset signals from neighboring columns of the same color, receiving the video signals from pixels generating the reset signals, and generating a plurality of modulation signals respectively corresponding to the differences between the reset signals and the video signals such that each succeeding one of the plurality of modulation signals is activated in response to the previous modulation signal; and

digital signal output means in signal communication with the correlated double sampling means for generating a corresponding digital signal responsive to the instant of time when the logic state of the finally activated modulation signal is changed among the plurality of modulation signals,

wherein the correlated double sampling means is disposed for generating a modulation signal of a first column, which is activated when the difference between the reset signal and the video signal from the first column reaches a reference level in response to a ramp signal, and for generating a modulation signal of the next same-color column, which is activated when the difference of the reset signal and the video signal of the next same-color column reaches the reference level in response to the ramp signal and the activation of the first column modulation signal.

16. The image sensing device of claim 15, the correlated double sampling means comprising:

a first switch disposed for transferring the ramp signal;

a second switch disposed for transferring the reset signals and the video signals; and

a plurality of correlated double sampling circuits disposed for generating the differences between the reset signals and the video signals and generating the modulation signals activated when the differences reach the reference level in response to the ramp signal, respectively, the correlated double sampling circuits being included in the respective columns, the second switch being tuned off when the modulation signal generated in the previous column is activated.

17. The image sensing device of claim 16, wherein each of the plurality of correlated double sampling circuits comprises:

a first capacitor connected between the output terminal of the second switch and a first node;

a second capacitor connected between the output terminal of the second switch and the output terminal of the first switch;

an amplifier comparing the signal of the first node with the reference level and amplifying the compared result; and

a third switch connected between the first node and the output terminal of the amplifier, a corresponding reset signal being transmitted to the first capacitor when the third switch is turned on, a corresponding video signal being transmitted to the first capacitor when the third switch is turned off.

18. The image sensing device of claim 15, further comprising:

first generator means for generating reset signals and video signals of respective columns in a selected row in an APS array in which pixels are arranged in a two- dimensional matrix form;

first receiver means for receiving reset signals from neighboring columns of the same color;

second receiver means for receiving video signals from pixels generating the reset signals;

second generator means for generating modulation signals respectively corresponding to the differences between the reset signals and the video signals such that each of the modulation signals is activated according to activation of the previous modulation signal; and

third generator means for generating a corresponding digital signal based on the instant of time when the logic state of the finally activated modulation signal among the modulation signals is changed.