Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

• US 7,646,666 B2
• Filed: 03/12/2009
• Issued: 01/12/2010
• Est. Priority Date: 02/17/2000
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Mangan, John S., Craig, Jeffrey G.
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/402,955
• Publication Number:
  US 20090175082A1
• Time in Patent Office: 306 Days
• Field of Search: 365/230.06, 365/230.03
• US Class Current: 365/230.06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Claims

1. A memory system, comprising:

at least two groups of re-programmable non-volatile memory cells, wherein the memory cells of the at least two groups are divided into a number of blocks of memory cells that are individually operable to store a given quantity of data, a plurality of the blocks of memory cells being designated to store user data,

a memory controller; and

a record stored in the memory system that contains non-overlapping ranges of logical addresses of the designated blocks of memory cells within each of the at least two groups, thereby to allow the controller to determine, from a received logical block address, one of the at least two groups in which a corresponding designated block of memory cells is located and the address of the corresponding designated block of memory cells within the determined group.

2. The memory system of claim 1, wherein a number of the plurality of blocks of memory cells designated to store user data is different among at least some of the at least two groups of memory cells.

3. The memory system of claim 1, wherein the record is stored within one of the at least two groups of memory cells.

4. The memory system of claim 1, wherein the at least two groups of memory cells are formed on at least two respective integrated circuit chips.

5. The memory system of claim 1, wherein

the logical address ranges are continuous,

the record includes a maximum logical block address for the logical address ranges for each of the at least two groups of memory cells, and

the memory controller operates to determine from the received logical block address the one of the at least two groups in which the corresponding designated block of memory cells is located by performing a subtraction of the maximum logical block addresses.

6. The memory system according to any one of claims 1-5, wherein the memory cells of at least the plurality of blocks of memory cells designated to store user data are individually operated with more than two storage states in order to store more than one bit of data per memory cell.

7. The memory system according to any one of claims 1-5, wherein the memory controller operates to program user data in parallel into more than one of the plurality of blocks of memory cells designated to store user data.

8. The memory system according to any one of claims 1-5, wherein said at least two groups of memory cells and the memory controller are positioned within an enclosed memory card having electrical contacts thereon that match electrical contacts of a receptacle of a host system, the memory card thereby being removably connectable with the host system.