Method for decreasing program disturb in memory cells

• US 7,649,771 B2
• Filed: 10/19/2007
• Issued: 01/19/2010
• Est. Priority Date: 12/21/2006
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Liu, Jianchang, Tan, Leong Seng, Miu, Kenneth, Zhong, Can
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US11/875,822
• Publication Number:
  US 20080151667A1
• Time in Patent Office: 823 Days
• Field of Search: 365/185.02, 365/185.18, 365/185.19, 365/195.24, 365/185.26, 365/185.28
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

The present invention provides a method for decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensures programming memory cell normally; selecting two parameters from the initial programming condition as variables for a program disturb test; performing the program disturb test to the memory cell for at least two combined values of the variables; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb in memory cells and can be performed easily.

Claims

1. A method for decreasing program disturb in memory cells, comprising:

finding an initial programming condition that ensures programming a memory cell normally;

selecting two parameters from the initial programming condition as variables for a program disturb test;

performing the program disturb test to the memory cell for at least two combined values of the variables;

obtaining a programming condition with minimum program disturb based on a result of the program disturb test; and

applying the programming condition with minimum program disturb during programming the memory cell.

2. The method according to claim 1, wherein the step of finding an initial programming condition that ensures programming the memory cell normally includes:

measuring an initial threshold voltage of transistor in the memory cell;

performing a programming operation to the memory cell by keeping a base of the transistor in the memory cell being grounded and a source of the transistor in the memory cell being floated, applying a voltage of 10V to a gate, and applying a pulse voltage of by to a drain of the transistor in the memory cell, the pulse voltage having one pulse and a pulse width of 0.5 μ

s;

measuring the threshold voltage of the transistor in the memory cell again;

determining whether a difference in the threshold voltages is larger than a nominal value of the transistor in the memory cell;

performing an erase operation to the memory cell to drop the threshold voltage of the transistor in the memory cell to the initial voltage if the difference in the threshold voltages is smaller than the nominal value and hence the memory cell is unable to be programmed normally, and then returning to the step of performing a programming operation;

performing the erase operation to the memory cell to drop the threshold voltage of the transistor in the memory cell to the initial voltage if the difference in the threshold voltages reaches the nominal value and hence the set drain voltage is able to program the memory cell normally; and

recording at least two drain voltages and the number of pulses and the pulse width thereof, the source voltage, the base voltage and the gate voltage capable of programming the memory cell normally as the initial programming condition.

3. The method according to claim 1, wherein the parameters comprise pulse width and the number of pulses.

4. The method according to claim 1, wherein the program disturb test includes the following steps:

programming the memory cell by setting combined values for the variables and maintaining other parameters in the initial programming condition unchanged;

measuring and recording the program disturb;

determining whether other combined values to be set to the variables remain;

returning to the step of programming the memory cell if other combined values to be set to the variables remain;

otherwise, completing the disturb test.

5. The method according to claim 1, wherein the programming condition with minimum program disturb is a set of values corresponding to each program parameter capable of minimizing the program disturb in memory cells.

6. The method according to claim 2, wherein the nominal value is 2V.

7. The method according to claim 2, wherein the drain voltage at which the memory cell is programmed normally is 3.6V, 3.8V, 4.0V and 4.2V.

8. The method according to claim 2, wherein the initial programming condition is as follows:

the base of the transistor in the memory cell is grounded, the source is floated, a voltage of 10V is applied to the gate, and a pulse voltage of 3.6V, 3.8V, 4.0V or 4.2V is applied to the drain, the pulse voltage having a pulse width of 0.5 μ

s and one pulse.

9. The method according to claim 4, wherein the combined values for the variables are as follows:

the number of pulses is one and the pulse width is 0.5 μ

s, the number of pulses is one and the pulse width is 1 μ

s, the number of pulses is one and the pulse width is 1.5 μ

s, the number of pulses is one and the pulse width is 2 μ

s, the number of pulses is two and the pulse width is 1 μ

s and the number of pulses is two and the pulse width is 2 μ

s.