Device for processing access concurrence to shared memory

• US 7,650,468 B2
• Filed: 11/29/2004
• Issued: 01/19/2010
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
• Original Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
• Inventors: Hirano, Tetsuya
• Primary Examiner(s): Elmore; Stephen C
• Assistant Examiner(s): Giardino, Jr.; Mark A
• Application Number:
  US10/583,868
• Publication Number:
  US 20070113024A1
• Time in Patent Office: 1,877 Days
• Field of Search: 711/150, 712/35, 712/36, 846/02
• US Class Current: 711/150
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G10H 2210/155 Musical effects
• CPC Class Codes: G10H 2230/031 Use of cache memory for electrophonic musical instrument processes, e.g. for improving processing capabilities or solving interfacing problems
• CPC Class Codes: G10H 7/004 with one or more auxiliary processor in addition to the main processing unit

Abstract

A data processor that allows a CPU to access an external memory in an interval between data accesses from a DSP having a variable data length. In a case where a 24-bit mode is set, when a determination section determines that the DSP is accessing the external memory, a control section commands to place an access from the CPU to the external memory in a wait state. In a case where a 16-bit mode is set, the control section commands an address-data switching section, allowing the CPU to access the external memory by utilizing a third bus cycle, which is free.

Claims

1. A data processor, comprising:

a CPU configured to control an entire system;

a DSP configured to perform preset processing, to have at least two bus cycles in a unit of one data access, and to use a selectable number of the bus cycles in the unit of one data access; and

an external memory configured to be accessed by the DSP and to be accessed through the DSP by the CPU, wherein

a data word length accessed by the DSP at the external memory is variable, and

the DSP includes

a determination unit configured to determine whether the DSP is accessing the external memory;

a control unit configured to determine whether the CPU is allowed to access the external memory, based on a signal from the determination unit; and

a switching unit configured to perform a switching operation of an address and a data in connection with the external memory according to a command from the control unit, and to input and to output the address and the data based on the switching operation,

wherein when the DSP accesses the external memory using a maximum number of the bus cycles in a unit of data access wherein the DSP actually accesses the external memory, access from the CPU to the external memory is placed in a wait state until a subsequent unit of data access commences, and

when the DSP does not access the external memory using the maximum number of the bus cycles in said unit of data access wherein the DSP actually accesses the external memory, access from the CPU to the external memory is constantly allowed during said unit of data access.

2. A data processor, comprising:

a CPU configured to control an entire system;

a sound source configured to supply a musical tone signal;

a DSP configured to perform preset processing to apply a desired effect to the musical tone signal supplied from the sound source, to have at least two bus cycles in a unit of one data access with respect to signal processing of the musical tone signal, and to use a selectable number of bus cycles in the unit of one data access; and

an external memory configured to be accessed by the DSP and to be accessed through the DSP by the CPU, wherein

a data word length accessed by the DSP at the external memory is variable, and

the DSP includes

a determination unit configured to determine whether the DSP is accessing the external memory;

a control unit configured to determine whether the CPU is allowed to access the external memory, based on a signal from the determination unit; and

a switching unit configured to perform a switching operation of an address and a data in connection with the external memory according to a command from the control unit, and to input and to output the address and the data based on the switching operation,

wherein when the DSP accesses the external memory using a maximum number of the bus cycles in a unit of data access wherein the DSP actually accesses the external memory, access from the CPU to the external memory is placed in a wait state until a subsequent unit of data access commences, and

when the DSP does not access the external memory using the maximum number of the bus cycles in said unit of data access wherein the DSP actually accesses the external memory, access from the CPU to the external memory is constantly allowed during said unit of data access data.

3. A data processor having a fixed number of memory access timings per sampling cycle, the data processor comprising:

a plurality of DSPs configured to access a single external memory in a single package;

a read/write control unit configured so that when each of the DSPs issues a read command or a write command at a same time, none of the commands from the DSPs are performed and when only one of the DSPs issues the read command or the write command, the command from the only one DSP is performed;

an access determination unit configured so that when each of the DSPs issues the read command or the write command at the same time, none of the DSPs are not allowed to access the external memory and when the only one of the DSPs issues the read command or the write command, the only one DSP is allowed to access the external memory;

a first selector configured to output an address from the allowed DSP in response to a determination signal from the access determination unit; and

a second selector configured to output data from the allowed DSP in response to the determination signal, wherein

each of the DSPs includes a control unit configured to acquire data from the external memory in response to the determination signal from the access determination unit, and

the read/write control unit does not access the external memory when each of the DSPs simultaneously issues a command.

4. A data processor having a fixed number of memory access timings per sampling cycle, the data processor comprising:

a plurality of DSPs configured to access a single external memory in a single package, the external memory storing musical tone waveform data;

a read/write control unit configured so that when each of the DSPs issues a read command or a write command at a same time, none of the commands from the DSPs are performed and when only one of the DSPs issues the read command or the write command, the command from the only one DSPs is performed;

an access determination unit configured so that when each of the DSPs issues the read command or the write command at the same time, none of the DSPs are not allowed to access the external memory and when only one of the DSPs issues the read command or the write command, the only one DSP is allowed to access the external memory;

a first selector configured to output an address from the allowed DSP in response to a determination signal from the access determination unit; and

a second selector configured to output data from the allowed DSP in response to the determination signal, wherein

each of the DSPs includes a control unit configured to acquire data from the external memory in response to the determination signal from the access determination unit, and

the read/write control unit does not access the external memory when each of the DSPs simultaneously issues a command.