Integrated circuit package system including stacked die

• US 7,652,376 B2
• Filed: 09/22/2008
• Issued: 01/26/2010
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Ha, Jong-Woo, Park, Soo-San, Lee, Sang-Ho, Kwon, Hyeog Chan
• Primary Examiner(s): Potter; Roy K
• Application Number:
  US12/235,521
• Publication Number:
  US 20090014899A1
• Time in Patent Office: 491 Days
• Field of Search: 257/777, 257/686, 257/E23.141, 257/701, 257/737
• US Class Current: 257/737
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.

Claims

1. An integrated circuit package system comprising:

a die with bond pads formed on the die and a planarized bottom exposed surface;

a solder bump deposited on one or more bond pads;

a mold compound formed on the die, the mold compound embedding the bond pads and the solder bump; and

a recess formed into the edges of the mold compound to expose a portion of the solder bump.

2. The system as claimed in claim 1 wherein the exposed portion of the solder bump further comprises:

a top portion of the solder bump.

3. The system as claimed in claim 1 wherein the recess is above the bond pads.

4. The system as claimed in claim 1 further comprising:

a wire bond attached to the exposed portion of the solder bump in the recess.

5. An integrated circuit package system comprising:

a die with bond pads formed on the die;

a solder bump deposited on one or more bond pads;

a mold compound formed on the die, the mold compound embedding the bond pads and the solder bump;

a recess formed into the edges of the mold compound to expose a portion of the solder bump;

a printed circuit board connected to a bottom exposed surface of the die; and

electrical connectors connected to the exposed portion of the solder bump and the printed circuit board, wherein a combined height of the mold compound and the die is at least greater than a height of the electrical connectors.

6. The system as claimed in claim 5 wherein the electrical connectors further comprises:

wire bonds attached to the exposed portion of the solder bump; and

bond wires electrically coupled to the wire bonds and the printed circuit board.

7. The system as claimed in claim 5 further comprising:

a semiconductor structure mounted on the mold compound.

8. The system as claimed in claim 7 further comprising:

a layer of laminate film deposited between the semiconductor structure and the mold compound.

9. The system as claimed in claim 5 further comprising:

an encapsulant encapsulating the electrical connectors, the die, and the mold compound.