Methods and systems for generating latch clock used in memory reading

• US 7,652,938 B2
• Filed: 10/23/2006
• Issued: 01/26/2010
• Est. Priority Date: 03/22/2005
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Tseng, Jui-Hsing
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US11/551,771
• Publication Number:
  US 20070041253A1
• Time in Patent Office: 1,191 Days
• Field of Search: 365/194, 365/189.07, 365/191, 365/230.08, 365/189.05, 365/189.08, 365/233, 365/189.01
• US Class Current: 365/194
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. Varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned. Finally, the latch clock is generated according to the delay parameter and the internal clock.

Claims

1. A method for generating, from an internal clock, a latch clock used in reading a memory, the method comprising:

storing data with a first logic level into a first address of the memory and data with a second logic level into a second address of the memory;

generating a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory;

varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned; and

generating the latch clock according to the delay parameter and the internal clock.

2. The method as claimed in claim 1, further comprising reading data stored in the memory with reference to the latch clock.

3. The method as claimed in claim 1, wherein the first memory address and the second memory address are within a page of the memory.

4. The method as claimed in claim 1, wherein the first memory address and the second memory address are contiguous.

5. The method as claimed in claim 1, wherein the frequency of the internal clock is integral times of a frequency of the read data signal.

13. The method as claimed in claim 1, wherein the data stored into the first address of the memory is data “

1” and

the data stored into the second address of the memory is data “

0”

.

16. The method as claimed in claim 1, wherein the data respectively stored in the first address and the second address are complementary.

18. The method as claimed in claim 1, wherein the data respectively stored in the first address and the second address are continuously accessed without closing or opening the page.

6. A memory subsystem, comprising:

a memory; and

a memory controller comprising an internal clock, the memory controller operative in a calibration mode to store data with a first logic level into a first address of the memory, to store data with a second logic level into a second address of the memory, to generate a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory, to adjust a delay parameter until any edge of the read data signal and at least one edge of the internal clock signal are aligned, and to generate a latch clock according to the delay parameter and the internal clock.

7. The memory subsystem as claimed in claim 6, wherein the memory controller reads data stored in the memory with reference to the latch clock in a normal mode.

8. The memory subsystem as claimed in claim 6, wherein the memory comprises a page, and the first and the second addresses are within the page.

9. The memory subsystem as claimed in claim 6, wherein the first memory address and the second memory address are contiguous.

10. The memory subsystem as claimed in claim 6, wherein the frequency of the internal clock is integral times of a frequency of the read data signal.

11. The memory subsystem as claimed in claim 6, wherein the memory controller comprises:

a phase detector operative to receive the read data signal, and to output a phase determined signal in assertion state when at least an edge of the read data signal is aligned with at least one edge of the internal clock; and

a control circuit operative to change the delay parameter when the phase determined signal is in deassertion state.

14. The memory subsystem as claimed in claim 6, wherein the data stored into the first address of the memory is data “

1” and

the data stored into the second address of the memory is data “

0”

.

17. The memory subsystem as claimed in claim 6, wherein the data respectively stored in the first address and the second address are complementary.

19. The memory subsystem as claimed in claim 6, wherein the data respectively stored in the first address and the second address are continuously accessed without closing or opening the page.

12. A memory subsystem, comprising:

a memory; and

a memory controller providing a latch clock and accessing the memory with reference to the latch clock, comprising;

means for storing data with a first logic level into a first address of the memory, and storing data with a second logic level into a second address of the memory;

means for generating a read data signal by issuing continuous read commands to repeatedly retrieve the data at the first and the second addresses of the memory;

means for varying a delay parameter until any edge of the read data signal and at least one edge of the internal clock signal are aligned; and

means for generating the latch clock according to the delay parameter and the internal clock.

15. The memory subsystem as claimed in claim 12, wherein the data stored into the first address of the memory is data “

1” and

the data stored into the second address of the memory is data “

0”

.