Methods and systems for generating latch clock used in memory reading

  • US 7,652,938 B2
  • Filed: 10/23/2006
  • Issued: 01/26/2010
  • Est. Priority Date: 03/22/2005
  • Status: Active Grant
First Claim
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1. A method for generating, from an internal clock, a latch clock used in reading a memory, the method comprising:

  • storing data with a first logic level into a first address of the memory and data with a second logic level into a second address of the memory;

    generating a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory;

    varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned; and

    generating the latch clock according to the delay parameter and the internal clock.

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