Method of packaging a semiconductor device and a prefabricated connector

• US 7,655,502 B2
• Filed: 07/28/2009
• Issued: 02/02/2010
• Est. Priority Date: 11/17/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mangrum, Marc A., Burch, Kenneth R.
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US12/510,369
• Publication Number:
  US 20090286390A1
• Time in Patent Office: 189 Days
• Field of Search: 438/106, 438/107, 438/109, 438/118, 438/119, 438/127
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8192 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.

Claims

1. A method of packaging a first device having a first major surface and a second major surface, comprising:

forming a dielectric layer over the first major surface a first device;

forming a first via in the dielectric layer;

forming a second via in the dielectric layer;

forming a first seed layer in the first via;

forming a second seed layer in the second via;

placing at least a portion of a first external connector over the dielectric layer, wherein the forming the first seed layer and the placing at least a portion of the first external connector couples the first external connector to the first device;

plating the first seed layer to form a first interconnect;

plating the second seed layer to form a second interconnect; and

coupling the second interconnect to a second external connector.

2. The method of claim 1, wherein the first external connector and the second external connector are different types of connectors.

3. The method of claim 2, wherein the first external connector comprises a prefabricated connector and the second external connector comprises a solder ball.

4. The method of claim 3, wherein the first external connector and the second external connector are both formed over the first major surface of the first device, wherein the first major surface comprises contacts.

5. The method of claim 4, wherein the first external connectors are formed over a first major surface of the first device, wherein the first major surface comprises contacts, and the second external connector is formed over the second major surface of the first device, wherein the second major surface is opposite the first major surface.

6. The method of claim 1, wherein the first seed layer is formed after the step of placing at least a portion of the first external connector.

7. The method of claim 1, wherein the first seed layer is formed before the step of placing at least a portion of the first external connector.