MEMS device and interposer and method for integrating MEMS device and interposer

• US 7,655,538 B2
• Filed: 09/19/2007
• Issued: 02/02/2010
• Est. Priority Date: 01/02/2001
• Status: Active Grant

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Sawyer, William D.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US11/857,720
• Publication Number:
  US 20080003779A1
• Time in Patent Office: 867 Days
• Field of Search: 438/459, 438/FOR.105, 148/DIG.12, 216/2
• US Class Current: 438/459
• CPC Class Codes: B81B 2203/0307 Anchors
• CPC Class Codes: B81B 7/0048 between the MEMS die and the substrate

Abstract

A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least partially define the MEMS device, bonding the SOI wafer to an interposer by direct boding, removing the handle layer of the SOI wafer, removing the oxide layer of the SOI wafer, and further etching the device layer of the SOI wafer to define the MEMS device. A structure manufactured according to the above described processes includes an interposer comprising an SOI wafer and a MEMS device mounted on the interposer. The MEMS device comprises posts extending from a silicon plate. The MEMS device is directly mounted to the interposer by bonding the posts of the MEMS device to the device layer of the interposer.

Claims

1. A method for manufacturing a Microelectromechanical Systems (MEMS) assembly, said method comprising:

obtaining an SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said SOI wafer to at least partially define said MEMS device;

obtaining an interposer wafer;

bonding said SOI wafer to said interposer wafer in a way such that said device layer of said SOI wafer faces said interposer wafer and a portion of the dielectric layer is adjacent said at least partially defined MEMS device;

removing said handle layer of said SOI wafer; and

removing completely at least the portion of said dielectric layer of the SOI wafer adjacent said at least partially defined MEMS device.

2. A method according to claim 1 further comprising:

etching said device layer of said SOI wafer to further define said MEMS device.

3. A method according to claim 2, wherein said etching said device layer of said SOI wafer to further define said MEMS device is performed by inductively coupled plasma (ICP) etch.

4. A method according to claim 2, wherein said etching said device layer of said SOI wafer to further define said MEMS device defines a proof mass.

5. A method of claim 1 further comprising etching said interposer wafer to further define a structure of said interposer wafer.

6. A method of claim 1, wherein the dielectric layer of the SOI wafer comprises silicon dioxide.

7. A method according to claim 1, wherein said bonding said SOI wafer to said interposer wafer comprises intermediate-layer bonding, wherein said intermediate layer material is adapted for wafer-to-wafer bonding.

8. A method according to claim 1, wherein said device layer is doped with a dopant concentration adapted to form said MEMS device.

9. A method according to claim 1, wherein said etching said device layer of said SOI wafer to at least partially define said MEMS device comprises etching said device layer to define posts of said MEMS device.

10. A method according to claim 1, wherein said etching said device layer of said SOI wafer to at least partially define said MEMS device comprises a mesa etch.

13. A method according to claim 1, wherein said device layer of said SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

16. The method of claim 1, comprising removing completely said dielectric layer of the SOI wafer.

11. A method for manufacturing a Microelectromechanical Systems (MEMS) assembly, said method comprising:

obtaining an SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said SOI wafer to partially define said MEMS device;

obtaining an interposer wafer;

bonding said SOI wafer to said interposer wafer in a way such that said device layer of said SOL wafer faces said interposer wafer and a portion of the dielectric layer is adjacent said at least partially defined MEMS device;

removing said handle layer of said SOI wafer;

removing completely at least the portion of said dielectric layer of the SOI wafer adjacent said at least partially defined MEMS device; and

etching said device layer of said SOI wafer to further define said MEMS device.

14. A method according to claim 11, wherein said device layer of said SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

17. The method of claim 11, comprising removing completely said dielectric layer of the SOI wafer.

12. A method for manufacturing Microelectromechanical Systems (MEMS) devices, said method comprising:

obtaining an SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said SOI wafer to define an array of sets of structural posts, wherein each set of structural post includes at least one structure post;

obtaining an interposer wafer;

bonding said SOI wafer to said interposer wafer in a way such that said device layer of said SOI wafer faces said interposer wafer and a portion of the dielectric layer is adjacent said at least partially defined MEMS device;

removing said handle layer of said SOI wafer;

removing completely at least the portion of said dielectric layer of the SOI wafer adjacent said at least partially defined MEMS device;

etching said device layer of said SOI wafer to define an array of said MEMS devices; and

separating the result structure into individual MEMS devices.

15. A method according to claim 12, wherein said device layer of said SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

18. The method of claim 12, comprising removing completely said dielectric layer of the SOI wafer.