Localized biasing for silicon on insulator structures

• US 7,659,152 B2
• Filed: 08/30/2004
• Issued: 02/09/2010
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zahurak, John K., Gonzalez, Fernando
• Primary Examiner(s): Booth; Richard A.
• Application Number:
  US10/930,001
• Publication Number:
  US 20050032284A1
• Time in Patent Office: 1,989 Days
• Field of Search: 438151-166, 257/E21.561
• US Class Current: 438/155
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/036 the capacitor extending under the transistor

Abstract

A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

Claims

1. A method of forming a silicon-on-insulator structure, comprising:

providing a silicon-on-insulator substrate;

forming a recess in an insulator layer disposed on the silicon-on-insulator substrate;

depositing a conductor in the recess that is electrically isolated from the substrate; and

forming an active semiconductor device positioned directly over and having a body region in a direct abutting relationship with the conductor, wherein the semiconductor device is contiguous with the silicon-on-insulator substrate.

2. The method of claim 1, wherein providing the silicon-on-insulator substrate includes forming the insulator layer by forming a buried oxide layer in the substrate.

3. The method of claim 2, wherein forming the recess includes etching into the buried oxide layer to form the recess.

4. The method of claim 1, wherein depositing the conductor includes depositing a conductive polysilicon in the recess.

5. The method of claim 1, wherein forming a semiconductor device includes forming a body region of the semiconductor device in electrical contact with the conductor, the conductor being adapted to provide a biasing voltage to the body region.

6. The method of claim 5, wherein depositing the conductor includes connecting the conductor to a bias voltage source.

7. A method, comprising:

providing a substrate;

forming an insulator layer on the substrate;

forming a plurality of mutually spaced-apart conductors in the insulator layer, wherein the conductors are individually configured to be coupled to a selected voltage potential and are electrically insulated from the substrate;

forming a silicon layer abutting the insulator layer and the conductors;

forming an active integrated circuit device having a body region in the silicon layer; and

wherein forming the active integrated circuit device includes forming the body region positioned directly above and abutting a selected one of the conductors to provide electrical contact with the conductors.

8. The method of claim 7, wherein providing the substrate includes fabricating at least one further integrated circuit device in the substrate.

9. The method of claim 8, wherein forming the integrated circuit device includes electrically connecting the integrated circuit device with the further integrated circuit device.

10. The method of claim 7, wherein forming the conductor includes planarizing an upper surface of the conductor and insulator layer, and thereafter forming the silicon layer on the planarized upper surface.

11. The method of claim 7, wherein forming the conductor includes annealing conductive material in the insulator layer.

12. The method of claim 7, wherein forming the insulator layer includes forming a recess in the insulator layer.

13. The method of claim 12, wherein forming the conductor includes depositing a conductive polysilicon in the recess.

14. The method of claim 12, wherein forming the recess includes etching a recess to a depth of about 500 angstroms.

15. A method, comprising:

providing a substrate;

forming an insulator layer on the substrate;

depositing a patterned resist on the insulator layer;

etching the insulator layer in areas of the insulator not covered by resist to form a plurality of mutually spaced-apart recesses;

depositing conductors in the recesses, wherein the conductors are configured to be individually coupled to selected voltage potentials and are electrically insulated from the substrate;

forming a silicon layer abutting the insulator layer and the conductor;

forming an active integrated circuit device having a body region in the silicon layer; and

wherein forming the integrated circuit device includes forming the body region positioned directly above and abutting a selected one of the conductors to provide electrical contact with the conductor.

16. The method of claim 15, wherein forming the silicon layer includes planarizing an upper surface of the insulator layer and the conductor.

17. The method of claim 16, wherein planarizing includes chemical-mechanical planarizing.

18. The method of claim 15, wherein depositing the conductor includes depositing a conductive material in the recess and removing the resist.

19. The method of claim 15, wherein forming the integrated circuit includes doping a first source/drain region of the silicon layer and doping a second source/drain region of the silicon layer.

20. The method of claim 19, wherein the first source/drain region and the second source/drain region are physically spaced and electrically open from the conductor.

21. A method of forming a silicon-on-insulator device, comprising:

providing a substrate;

forming an insulator in contact with the substrate;

patterning the insulator to form more than one conductive portion within the insulator, the conductive portions being mutually spaced-apart and configured to provide a local voltage bias, wherein the conductive portions are electrically insulated from the substrate;

forming a silicon layer that abuts the insulator that contacts the insulator and the more than one conductive portion; and

forming at least one active integrated circuit device in the silicon layer that is positioned directly vertically above and having a body region in a direct abutting relationship with at least one of the conductive portions.

22. The method of claim 21, wherein patterning the insulator comprises planarizing the insulator and the at least one conductive portion.

23. The method of claim 21, wherein patterning the insulator comprises:

depositing a resist pattern on the insulator;

etching the insulator to form at least one recess;

removing the resist; and

depositing a conductive material into the at least one recess to form the at least one conductive portion.

24. The method of claim 23, wherein depositing a conductive material into the at least one recess comprises depositing a layer of polysilicon into the at least one recess.

25. The method of claim 21, wherein forming at least one integrated circuit device comprises forming at least one of a transistor, a charge storage device, and a logic circuit.

26. A method of forming a silicon-on-insulator semiconductor device, comprising:

providing a substrate;

forming an insulator in contact with the substrate;

forming a patterned conductor within the insulator defining a plurality of voltage biasing portions, wherein the patterned conductor is electrically insulated from the substrate;

applying a silicon layer on the insulator that abuts the insulator and the patterned conductor;

forming at least one active integrated circuit device in the silicon layer positioned directly vertically above and having a body region in a direct abutting relationship with one of the plurality of voltage biasing portions; and

coupling a discharge circuit to the at least one integrated circuit device.

27. The method of claim 26, wherein forming at least one integrated circuit device comprises forming an integrated circuit device that includes a body region.

28. The method of claim 27, wherein forming an integrated circuit device that includes a body region comprises coupling the discharge circuit to the body region.

29. The method of claim 26, wherein coupling a discharge circuit to the at least one integrated circuit device comprises coupling a charge storage device to the integrated circuit device.

30. The method of claim 29, wherein coupling a charge storage device to the integrated circuit device comprises coupling a switch to the charge storage device to interruptably couple the charge storage device to a selected potential.

31. The method of claim 26, wherein coupling a discharge circuit to the at least one integrated circuit device comprises coupling the discharge circuit to a ground potential.

32. The method of claim 30, wherein coupling a switch to the charge storage device comprises coupling a transistor to the charge storage device that couples the charge storage device to a ground potential.

33. A method of fabricating a silicon-on-insulator structure, comprising:

providing a substrate;

forming at least one active integrated circuit device on the substrate;

forming an insulator layer abutting the substrate;

providing at least one recess in the insulator layer and depositing a conductive material in the at least one recess to define at least one voltage biasing portion;

depositing a layer of a semiconductor material on the insulator layer and the at least one voltage biasing portion, wherein the at least one voltage biasing portion is electrically insulated from the substrate;

forming at least one active integrated circuit device positioned directly vertically above and having a body region in a direct abutting relationship with the voltage biasing portion; and

forming a discharge device coupled to the at least one integrated circuit device.

34. The method of claim 33, wherein forming at least one integrated circuit device on the substrate comprises forming an integrated circuit device having a body region that is further coupled to the discharge device.

35. The method of claim 33, wherein forming a discharge device coupled to the at least one integrated circuit device comprises forming a charge storage device that is coupled to a selected potential.

36. The method of claim 35, wherein forming a charge storage device that is coupled to a selected potential comprises forming the charge storage device that is interruptably coupled to a ground potential.

37. The method of claim 36, wherein forming the charge storage device to that is interruptably coupled to a ground potential comprises forming a transistor that may be interruptably biased to couple the charge storage device to the ground potential.

38. The method of claim 33, wherein forming a discharge device coupled to the at least one integrated circuit device comprises forming the discharge device and the at least one integrated circuit device at the same time.

39. The method of claim 35, wherein forming a charge storage device that is coupled to a selected potential comprises forming a capacitor coupled to a selected potential.

40. The method of claim 39, wherein forming a capacitor coupled to a selected potential includes coupling the capacitor to a charge sink.