Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor

• US 7,659,893 B1
• Filed: 10/02/2006
• Issued: 02/09/2010
• Est. Priority Date: 10/02/2006
• Status: Expired due to Fees

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Molnar, Steven E., Oberman, Stuart F., Minkin, Alexander L., Holmqvist, Peter B.
• Primary Examiner(s): Wu; Xiao M
• Assistant Examiner(s): Sonners; Scott E
• Application Number:
  US11/538,002
• Time in Patent Office: 1,226 Days
• Field of Search: 345/422
• US Class Current: 345/422
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/405 using Z-buffer
• CPC Class Codes: G06T 2200/28 involving image processing hardware

Abstract

At least two different processing sections in a graphics processors compute Z coordinates for a sample location from a compressed Z representation. The processors are designed to ensure that Z coordinates computed in any unit in the processor are identical. In one embodiment, the respective arithmetic circuits included in each processing section that computes Z coordinates are “bit-identical,” meaning that, for any input planar Z representation and coordinates, the output Z coordinates produced by the circuits are identical to each other.

Claims

1. A graphics processor comprising:

a plane equation module to receive vertex information for a plurality of primitives, each primitive covering one or more of a plurality of tiles, and to generate a compressed Z representation corresponding to each primitive, each compressed Z representation being associated with at least one tile covered by the corresponding primitive;

a first processing section subsequent to the plane equation module, the first processing section including a first arithmetic circuit to compute a first Z coordinate for a sample location within a first tile from a first compressed Z representation associated with the first tile;

a second processing section subsequent to the plane equation module, the second processing section including a second arithmetic circuit to compute a second Z coordinate for a sample location within the first tile from a second compressed Z representation associated with the first tile; and

a third processing section subsequent to the plane equation module, the third processing section to receive the first Z coordinate from the first processing section and the second Z coordinate from the second processing section and to compare the first Z coordinate and the second Z coordinate,

wherein the first arithmetic circuit and the second arithmetic circuit are bit-identical to each other.

2. The graphics processor of claim 1 wherein the compressed Z representation is a planar Z representation.

3. The graphics processor of claim 1 wherein the first processing section is a processing core to execute a pixel shader and the second processing section is a raster operations unit.

4. The graphics processor of claim 1 wherein the first processing section is a raster operations unit and the second processing section is a frame buffer interface.

5. The graphics processor of claim 1 wherein the first processing section is a processing core to execute a pixel shader and the second processing section is a texture processing unit.

6. The graphics processor of claim 1 wherein the first processing section is a texture processing unit and the second processing section is a frame buffer interface.

7. The graphics processor of claim 2 wherein the planar Z representation includes coefficients A, B, and C for a plane equation of the form Z(x, y)=A*x+B*y+C, where (x, y) are screen coordinates of a sample in the tile.

8. The graphics processor of claim 7 wherein the plane equation module further determines at least the coefficient C as a tile-specific coefficient.

9. A method of rendering an image in a graphics processor, the method comprising:

generating a first compressed Z representation corresponding to a first one of a plurality of primitives, the first compressed Z representation being associated with a tile covered by the first primitive;

with a first processing section, computing a first Z coordinate for a sample location within the tile from the first compressed Z representation using a first arithmetic circuit in a first processing section of the graphics processor;

generating a second compressed Z representation corresponding to a second one of the plurality of primitives, the second compressed Z representation being associated with the tile;

with a second processing section, computing a second Z coordinate for the sample location within the first tile from the second compressed Z representation using a second arithmetic circuit in a second processing section of the graphics processor, the second arithmetic circuit being bit-identical to the first arithmetic circuit;

with a third processing section, comparing the first Z coordinate and the second Z coordinate; and

performing a rendering operation that depends at least in part on the result of comparing the first Z coordinate to the second Z coordinate.

10. The method of claim 9 wherein obtaining a compressed Z representation includes:

generating, based on the primitive, plane equation coefficients A, B, and C for a plane equation of the form Z(x, y)=A*x+B*y+C, where (x, y) are screen coordinates of a sample in the tile,

wherein the plane equation coefficients A, B, and C are included in the compressed Z representation.

11. The method of claim 10 wherein at least the coefficient C is determined as a tile-specific coefficient.

12. The method of claim 9 further comprising

storing the first compressed Z representation in a frame buffer coupled to the graphics processor.

13. The method of claim 9 wherein the first processing section is a processing core to execute a pixel shader and the second processing section is a raster operations unit.

14. The method of claim 9 wherein the first processing section is a raster operations unit and the second processing section is a frame buffer interface.

15. The method of claim 9 wherein the first processing section is a processing core configured to execute a pixel shader and the second processing section is a texture processing unit.

16. The method of claim 9 wherein the first processing section is a texture processing unit and the second processing section is a frame buffer interface.

17. A graphics processor comprising:

a plane equation module to receive vertex information for a plurality of primitives, each primitive covering one or more of a plurality of tiles, and to generate a compressed Z representation corresponding to each primitive, each compressed Z representation being associated with at least one tile covered by the corresponding primitive;

a first processing section subsequent to the plane equation module, the first processing section including a first arithmetic circuit to compute a first Z coordinate for a sample location within a first tile from a first compressed Z representation associated with the first tile;

a second processing section subsequent to the plane equation module, the second processing section including a second arithmetic circuit to compute a second Z coordinate for a sample location within the first tile from a second compressed Z representation associated with the first tile; and

a third processing section subsequent to the plane equation module, the third processing section to receive the first Z coordinate from the first processing section and the second Z coordinate from the second processing section and to compare the first Z coordinate and the second Z coordinate.

18. The graphics processor of claim 17 wherein the first arithmetic circuit and the second arithmetic circuit are bit-identical to each other.

19. The graphics processor of claim 17 wherein the compressed Z representation is a planar Z representation.