Multi-core integrated circuit with shared debug port
First Claim
1. An integrated circuit, comprising:
- a plurality of logic cores;
a debug controller coupled to each of the plurality of logic cores;
a test access port coupled to the debug controller and configured to provide an external interface to the debug controller; and
a core mask register configured to store a value indicating a selected one or more of the plurality of logic cores, wherein the core mask register is writable via the test access port;
wherein the debug controller is configured to switch the selected one or more logic cores from a normal mode of execution to a debug mode;
wherein, while in the normal execution mode, each of the logic cores is configured to execute program instructions;
wherein, while in the debug mode, each of the logic cores is configured to perform debug operations controlled by the debug controller according to commands received via the test access port; and
wherein each of the logic cores is capable of operating in the normal execution mode simultaneously with at least another one of the logic cores operating in the debug mode.
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Accused Products
Abstract
A single test access port, such as a JTAG-based debug port may be utilized to perform debug operations on logic cores of a multi-core integrated circuit, such as a multi-core processor. The shared debug port may respond to a particular command to enter a debugging mode and may be configured to forward all commands and data to a debugging controller of the integrated circuit during debugging. A mask register may be used to indicate which logic cores of the multi-core integrated circuit should be debugged. Additionally, custom debugging commands may include mask or core select fields to indicate which logic cores should be affected by the particular command. Debugging mode may be initialized for one or more logic cores either externally, such as be asserted a DBREQ signal, or internally, such as by configuring one or more breakpoints.
104 Citations
20 Claims
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1. An integrated circuit, comprising:
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a plurality of logic cores; a debug controller coupled to each of the plurality of logic cores; a test access port coupled to the debug controller and configured to provide an external interface to the debug controller; and a core mask register configured to store a value indicating a selected one or more of the plurality of logic cores, wherein the core mask register is writable via the test access port; wherein the debug controller is configured to switch the selected one or more logic cores from a normal mode of execution to a debug mode; wherein, while in the normal execution mode, each of the logic cores is configured to execute program instructions; wherein, while in the debug mode, each of the logic cores is configured to perform debug operations controlled by the debug controller according to commands received via the test access port; and wherein each of the logic cores is capable of operating in the normal execution mode simultaneously with at least another one of the logic cores operating in the debug mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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storing a value in a core mask register of a multi-core integrated circuit via a test access port of the integrated circuit, wherein the value indicates a selected one or more of a plurality of logic cores of the integrated circuit; the multi-core integrated circuit receiving a debug request signal to request that the selected one or more of the plurality of logic cores of the integrated circuit switch from a normal mode of execution to a debug mode, wherein while in the debug mode, each selected logic core is configured to perform debug operations controlled by a debug controller of the integrated circuit according to debug commands received via the test access port; in response to receiving one or more debug commands, the debug controller issuing one or more debug operations to each of the selected one or more of the plurality of logic cores; and simultaneously with the selected one or more of the plurality of logic cores operating in the debug mode, the logic cores not selected to switch from the normal mode of execution to the debug mode remaining in normal execution mode and executing program instructions. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A computer system, comprising:
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a system memory; and a multi-core microprocessor coupled to the system memory, comprising; a plurality of processor cores; a debug controller coupled to each of the plurality of processor cores; a test access port coupled to the debug controller and configured to provide an external interface to the debug controller; and a core mask register configured to store a value indicating a selected one or more of the plurality of logic cores, wherein the core mask register is writable via the test access port; wherein the debug controller is configured to switch the selected one or more logic cores from a normal mode of execution to a debug mode; wherein, while in the normal execution mode, each of the logic cores is configured to execute program instructions; wherein, while in the debug mode, each of the logic cores is configured to perform debug operations controlled by the debug controller according to commands received via the test access port; wherein each of the logic cores is capable of operating in the normal execution mode simultaneously with at least another one of the logic cores operating in the debug mode.
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Specification