Non-sequentially configurable IC

• US 7,667,486 B2
• Filed: 12/08/2006
• Issued: 02/23/2010
• Est. Priority Date: 02/14/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Butts, Michael, Hutchings, Brad L., Teig, Steven
• Primary Examiner(s): Barnie, Rexford N
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/608,790
• Publication Number:
  US 20070241791A1
• Time in Patent Office: 1,173 Days
• Field of Search: 326 37- 41, 326/47, 716/16
• US Class Current: 326/38
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

Claims

1. An integrated circuit (IC) comprising:

a plurality of reconfigurable circuits, each reconfigurable circuit for reconfigurably performing a plurality of different operations;

wherein at least a first reconfigurable circuit receives a periodic reconfiguration signal that has a plurality of values during a design cycle of the IC, wherein an order of said values are different for at least two different design cycles, wherein the first reconfigurable circuit reconfigures at a first reconfiguration rate and does not always follow a same sequential progression through the plurality of operations.

2. The IC of claim 1, wherein not following a same sequential progression through the plurality of operations comprises performing a first operation before a second operation during a first time period and performing the second operation before the first operation during a second time period, wherein the first and second time periods start relative to a same particular transitional edge of a clock.

3. The IC of claim 1 further comprising a signal generator that generates said periodic reconfiguration signal, the periodic signal for selecting a set of configuration data sets for the first reconfigurable circuit, wherein the configuration data sets selected by the periodic signal cause the first reconfigurable circuit to non-sequentially progress through the plurality of operations.

4. An integrated circuit (IC) comprising:

a reconfigurable circuit for reconfigurably performing a plurality of operations; and

a signal generator that generates a periodic signal based on a clock signal and a programming signal, the periodic signal causing the reconfigurable circuit to receive different sequences of configuration data sets during different time periods, wherein each configuration data set specifies an operation from the plurality of operations that the reconfigurable circuit has to perform.

5. The IC of claim 4, wherein the programming signal causes the signal generator not to follow a particular sequential progression through a set of values that the signal generator produces.

6. The IC of claim 4, wherein the configuration data sets are stored in the IC.

7. The IC of claim 4, wherein the configuration data sets are stored in the first reconfigurable circuit.

8. A method of operating an integrated circuit (IC) comprising a reconfigurable circuit for reconfigurably performing a plurality of different operations, the method comprising:

generating a periodic signal based on a clock signal and a programming signal;

causing the reconfigurable circuit to receive different configuration data sets based on the periodic signal during different time periods; and

performing different operations by the reconfigurable circuit from the plurality of operations based on the received configuration data sets.

9. The method of claim 8, wherein the programming signal causes the signal generator not to follow a particular sequential progression through a set of values that the signal generator produces.

10. The method of claim 8, wherein the configuration data sets are stored in the IC.

11. A method of implementing an integrated circuit (IC) comprising a set of reconfigurable circuits, the method comprising:

providing a signal generator on the IC for receiving a clock signal and for generating a non-sequentially encoded periodic signal;

providing a storage in the IC for storing a plurality of configuration data sets upon which the reconfigurable circuits base their operation; and

providing a set of selection circuits in the IC for receiving the periodic signal and for selecting a set of the configuration data sets based on the periodic signal;

wherein at least one reconfigurable circuit performs a plurality of different operations based on its selected set of configuration data sets.

12. The method of claim 11, wherein providing storage in the IC for storing the configuration data comprises providing storage in each reconfigurable circuit for storing the configuration data.

13. The method of claim 11, wherein the selection circuits corresponding to each reconfigurable circuit are located inside the corresponding reconfigurable circuit.

14. The method of claim 11, wherein the set of reconfigurable circuits comprises a set of reconfigurable interconnect circuits, each reconfigurable interconnect circuit for configurably performing a set of connection operations.

15. The method of claim 14, wherein the set of reconfigurable circuits further comprises a set of reconfigurable logic circuits, each reconfigurable logic circuit for configurably performing a set of functions, wherein the interconnect circuits configurably connect the logic circuits.