Method and apparatus for increasing data transfer rates through a communication channel

• US 7,668,244 B2
• Filed: 06/29/2005
• Issued: 02/23/2010
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornelius, William P.
• Primary Examiner(s): Tran; Khanh C
• Application Number:
  US11/172,332
• Publication Number:
  US 20070002970A1
• Time in Patent Office: 1,700 Days
• Field of Search: 375/259, 375/285, 375/295, 375/316, 375/340, 375342-343, 375/360, 375/246, 375/253, 327/50, 327/63, 327/77
• US Class Current: 375/253
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission

Abstract

A system for receiving data on a communication channel. The system examines the state of a bit that was previously received on the channel. If the state of the previously received bit was high, the system looks for a falling edge while receiving a subsequent bit on the channel. Otherwise, the system looks for a rising edge while receiving the subsequent bit on the channel. While looking for a rising edge or looking for a falling edge, the system samples a signal on the channel at discrete time steps within a symbol interval, wherein the symbol interval is a time period during which the signal can change states. The specific discrete time step at which the signal changes state is associated with a specific decoded output symbol. Note that the signal can also convey information by not changing states. Also note that not all symbols require the same time to be transmitted, because some symbols can be associated with signal transitions that happen sooner, whereas other symbols can be associated with signal transitions that happen later.

Claims

1. A method for encoding a signal for transmission on a channel and receiving data on the channel, comprising:

using an encoder to;

read the state of a previously transmitted bit;

read a multi-bit value to be encoded;

if the state of the previously transmitted bit is high,

use an encoding table for a high state to select a discrete time step in a symbol interval which corresponds to the multi-bit value to be encoded, wherein the symbol interval specifies a time period during which a signal being used to transmit the symbol can change states; and

cause a transition from high-to-low or cause the signal to remain high at the selected discrete time step; and

otherwise, if the state of the previously transmitted bit is low,

use an encoding table for a low state to select a discrete time step in the symbol interval which corresponds to the multi-bit value to be encoded, and

cause a transition from low-to-high or cause the signal to remain low at the selected time step.

2. The method of claim 1, wherein after causing a transition from high-to-low or a transition from low-to-high, the method further comprises waiting for a minimum switching period before causing a subsequent transition.

3. The method of claim 1, wherein causing a transition from high-to-low or a transition from low to high at a selected discrete time step involves using a variable-delay circuit.

4. The method of claim 1, wherein receiving data on the channel involves:

using a decoder to;

examine a state of a bit that was previously received on the channel;

if the state of the previously received bit was high, look for a falling edge while receiving a subsequent bit on the channel;

otherwise, look for a rising edge while receiving the subsequent bit on the channel; and

wherein looking for at least one of a rising edge or a falling edge involves sampling the signal at discrete time steps within the symbol interval.

5. The method of claim 4, wherein looking for a rising edge involves using a different reference voltage or threshold voltage from the reference voltage or threshold voltage used when looking for a falling edge.

6. The method of claim 4, wherein looking for a rising edge or a falling edge involves:

sampling a signal on the channel at discrete time steps within a symbol interval, wherein the symbol interval specifies a time period during which the signal can change states;

wherein the specific discrete time step at which the signal changes state is associated with a specific encoded input which in turn is decoded;

wherein the signal can also convey information by not changing states; and

wherein not all bit patterns require the same time to be transmitted.

7. The method of claim 4, wherein the symbol interval represents a bit pattern.

8. An apparatus for encoding a signal and receiving data on a channel, comprising:

a transmitter with an encoder, wherein the encoder is configured to;

read the state of a previously transmitted bit;

read a multi-bit value to be encoded;

if the state of the previously transmitted bit is high, to

use an encoding table for a high state to select a discrete time step in a symbol interval which corresponds to the multi-bit value to be encoded, wherein the symbol interval specifies a time period during which a signal being used to transmit the symbol can change states; and

cause a transition from high-to-low or cause the signal to remain high at the selected discrete time step; and

otherwise, if the state of the previously transmitted bit is low, to

use an encoding table for a low state to select a discrete time step in the symbol interval which corresponds to the multi-bit value to be encoded; and

cause a transition from low-to-high or cause the signal to remain low at the selected time step.

9. The apparatus of claim 8, further comprising a receiver with a decoding mechanism, wherein the decoding mechanism is configured to:

examine a state of a bit that was previously received on the channel;

if the state of the previously received bit was high, to look for a falling edge while receiving a subsequent bit on the channel;

otherwise, to look for a rising edge while receiving the subsequent bit on the channel;

wherein while looking for at least one of a rising edge or a falling edge, the decoder is configured to sample a signal on the channel at discrete time steps within the symbol interval.

10. The apparatus of claim 9, wherein while looking for a rising edge the decoding mechanism is configured to use a different reference voltage or threshold voltage from the reference voltage or threshold voltage that the decoding mechanism is configured to use when looking for a falling edge.

11. The apparatus of claim 9, wherein while looking for a rising edge or looking for a falling edge, the decoder is configured to:

sample a signal on the channel at discrete time steps within a symbol interval, wherein the symbol interval specifies a time period during which the signal can change states;

wherein the specific discrete time step at which the signal changes state is associated with a specific encoded input which in turn is decoded;

wherein the signal can also convey information by not changing states; and

wherein not all bit patterns require the same time to be transmitted.

12. The apparatus of claim 9, wherein the symbol interval represents a bit pattern.

13. The apparatus of claim 8, wherein after causing a transition from high-to-low or a transition from low-to-high, the encoder is configured to wait for a minimum switching period before causing a subsequent transition.

14. The apparatus of claim 8, wherein causing a transition from high-to-low or a transition from low to high at a selected discrete time step involves using a variable delay circuit.

15. A computer system for receiving data on a channel, comprising:

a processor;

a memory;

a transmitter with an encoder, wherein the encoder is configured to;

read the state of a previously transmitted bit;

read a multi-bit value to be encoded;

if the state of the previously transmitted bit is high, to

use an encoding table for a high state to select a discrete time step in a symbol interval which corresponds to the multi-bit value to be encoded, wherein the symbol interval specifies a time period during which a signal being used to transmit the symbol can change states; and

cause a transition from high-to-low or cause the signal to remain high at the selected discrete time step; and

otherwise, if the state of the previously transmitted bit is low, to

use an encoding table for a low state to select a discrete time step in the symbol interval which corresponds to the multi-bit value to be encoded; and

cause a transition from low-to-high or cause the signal to remain low at the selected time step.

16. The computer system of claim 15, further comprising a receiver with a decoding mechanism, wherein the decoding mechanism is configured to:

examine a state of a bit that was previously received on the channel;

if the state of the previously received bit was high, to look for a falling edge while receiving a subsequent bit on the channel;

otherwise, to look for a rising edge while receiving the subsequent bit on the channel;

wherein while looking for at least one of a rising edge or a falling edge, the decoder is configured to sample a signal on the channel at discrete time steps within the symbol interval.

17. The computer system of claim 16, wherein while looking for a rising edge, the decoder is configured to use a different reference voltage or threshold voltage than the reference voltage or threshold voltage that the decoder is configured to use when looking for a falling edge.

18. The computer system of claim 16, wherein while looking for a rising edge or looking for a falling edge, the decoder is configured to:

sample a signal on the channel at discrete time steps within a symbol interval, wherein the symbol interval specifies a time period during which the signal can change states;

wherein the specific discrete time step at which the signal changes state is associated with a specific encoded input which in turn is decoded;

wherein the signal can also convey information by not changing states; and

wherein not all bit patterns require the same time to be transmitted.

19. The computer system of claim 16, wherein the symbol interval represents a bit pattern.

20. The computer system of claim 15, wherein after causing a transition from high-to-low or a transition from low-to-high, the encoder is configured to wait for a minimum switching period before causing a subsequent transition.

21. The computer system of claim 15, wherein causing a transition from high-to-low or a transition from low to high at a selected discrete time step involves using a variable delay circuit.