Increasing readout speed in CMOS APS sensors through block readout
First Claim
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1. A CMOS active-pixel image sensor, comprising:
- a pixel array arranged in rows and columns comprising a plurality of pixels having photosensors and in-pixel buffer transistors;
column output circuits for reading out signals corresponding to pixel values sampled from a selected row of pixels in the array, the column output circuits organized in a plurality of blocks, wherein all of the column output circuits in each of the blocks are connected to a respective one of a plurality of block output lines, and each of the blocks comprises a same number of greater than two column output circuits; and
greater than two block select switches, each of the block select switches connected between a respective one of the block output lines and a master output bus and configured to actively couple a single one of the block output lines to the master output bus at a time.
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Abstract
A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.
50 Citations
37 Claims
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1. A CMOS active-pixel image sensor, comprising:
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a pixel array arranged in rows and columns comprising a plurality of pixels having photosensors and in-pixel buffer transistors; column output circuits for reading out signals corresponding to pixel values sampled from a selected row of pixels in the array, the column output circuits organized in a plurality of blocks, wherein all of the column output circuits in each of the blocks are connected to a respective one of a plurality of block output lines, and each of the blocks comprises a same number of greater than two column output circuits; and greater than two block select switches, each of the block select switches connected between a respective one of the block output lines and a master output bus and configured to actively couple a single one of the block output lines to the master output bus at a time. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of reading out pixel signals from a CMOS pixel array having pixels arranged in rows and columns, the method comprising:
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activating a first block switch connecting a master output bus to a first plurality of greater than two output circuits respectively connected to a first plurality of the columns; reading out pixel signals one-at-a-time from the first plurality of output circuits via the master output bus; deactivating the first block switch; activating a second block switch connecting the master output bus to a second plurality of greater than two output circuits respectively connected to a second plurality of the columns; reading out pixel signals one-at-a-time from the second plurality of output circuits via the master output bus while the first block switch remains deactivated; deactivating the second block switch; activating a third block switch connecting the master output bus to a third plurality of greater than two output circuits respectively connected to a third plurality of the columns; and reading out pixel signals one-at-a-time from the third plurality of output circuits via the master output bus while the first and second block switches remain deactivated. - View Dependent Claims (9, 10, 11)
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12. A CMOS device, comprising:
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an array of pixels comprising column output lines, each of the column output lines coupled to at least one respective column of pixels of the array; column output circuits configured to provide a first set of signals associated with at least a first row of pixels of the array, each of the column output circuits coupled to at least a respective one of the column output lines; an array readout bus; and at least eight block select switches connected to the array readout bus, each of the block select switches connected to a respective one of a plurality of groups of the column output circuits and configured to provide the first set of signals to the array readout bus, wherein the block select switches are configured to allow only a single one of the plurality of groups of column output circuits to provide signals to the array readout bus at a time. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method of reading a row of pixels in a frame readout of a pixel array, comprising:
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activating a first group of block select switches to enable first column output signals in a first circuit block to be driven to an array readout bus, wherein the first column output signals in the first circuit block correspond to a first pixel of a first block of pixels in the row; activating a second group of block select switches to enable first column output signals and second column output signals in a second circuit block to be driven to the array readout bus, wherein the first column output signals and the second column output signals in the second circuit block correspond to first and second pixels, respectively, of a second block of pixels in the row, and the first pixel of the second block of pixels is adjacent to the first pixel of the first block of pixels; and activating a third group of block select switches to enable first column output signals in a third circuit block to be driven to the array readout bus, wherein the first column output signals in the third circuit block correspond to a first pixel of a third block of pixels in the row, and the first pixel of the third block of pixels is adjacent to the second pixel of the second block of pixels; wherein the first, second, and third blocks of pixels each contain the same number of pixels, and only one of the first, second, and third groups of block select switches are activated at a time. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37)
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Specification