Reliable generation of a device-specific value

• US 7,681,103 B2
• Filed: 06/01/2006
• Issued: 03/16/2010
• Est. Priority Date: 04/16/2002
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Devadas, Srinivas, Gassend, Blaise
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US11/421,588
• Publication Number:
  US 20060271793A1
• Time in Patent Office: 1,384 Days
• Field of Search: 714/807, 714/811, 714/752
• US Class Current: 714/752
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: G06F 2221/2121 Chip on media, e.g. a disk or tape with a chip embedded in its case
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06F 2221/2153 Using hardware token as a secondary aspect
• CPC Class Codes: G06Q 20/3674 involving authentication
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 2209/42 : Anonymization, e.g. involving pseudonyms
• CPC Class Codes: H04L 9/0897 : involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
• CPC Class Codes: H04L 9/3278 : using physically unclonable functions [PUF]

Abstract

A device-specific value is reliably generated in a device. In a first component of the device, a first digital value is generated that is substantially dependent fabrication variation among like device. Redundancy information is computed based on the first digital value. A subsequent digital value is later generated in the first component of the device. The first digital value is then determined in a second component of the device from the subsequent digital value and the redundancy information.

Claims

1. A method for repeatedly generating a device-specific value comprising:

in a first component of a device, generating a first digital value that is substantially dependent on fabrication variation among like devices, wherein the first digital value comprises a device-specific function of an input value inputted to a device;

computing redundancy information based on the first digital value;

in the first component of the device, generating a subsequent digital value; and

in a second component of the device, determining the first digital value from the subsequent digital value and the redundancy information.

2. The method of claim 1 repeating the steps of generating the subsequent digital value and determining the first digital value without requiring storage of the first digital value between repetitions.

3. The method of claim 1 wherein the first digital value and the subsequent digital value are dependent on at least one of measurement errors and environmental conditions of the device.

4. The method of claim 1 wherein the first component comprises a physically unknown function (PUF) component.

5. The method of claim 1 wherein the second component comprises error checking and correction (ECC) component.

6. The method of claim 1 wherein the second component comprises a processor implementing an error correction procedure.

7. The method of claim 1 wherein computing the redundancy information is performed in the device.

8. The method of claim 1 further comprising passing the redundancy information to the device.

9. A method for repeatedly generating an unpredictable device-specific value comprising:

generating a first value as an output of a first component of the device, wherein the first value comprises a device-specific function of an input value inputted to the device; and

computing an error correction value from the first value; and

regenerating the first value from an output of the first component and the error correction value.

10. The method of claim 9 wherein the output of the first component is dependent on fabrication parameters that vary among like devices.

11. The method of claim 10 wherein the output of the first component is dependent on at least one or measurement error and environmental conditions of the device.

12. An integrated circuit comprising:

a first component for providing a digital output value that depends on parameters that vary among like integrated circuits, the digital output value comprising a device-specific function of an input value inputted to the integrated circuit; and

a second component for accepting a digital output value from the first component and accepting redundancy information and determining a corrected output value.

13. The integrated circuit of claim 12 wherein the first component has characteristics that affect its output value and that vary among like integrated circuits.

14. The integrated circuit of claim 12 wherein the digital output value of the first component exhibits variation between different instances of providing a digital output.

15. The integrated circuit of claim 12 wherein the digital output value of the first component depends on environmental conditions.

16. The integrated circuit of claim 12 wherein the second component accepts an output value from the first component and determines the redundancy information from the output value.

17. The integrated circuit of claim 12 wherein the first component comprises a physically unpredictable function (PUF) module.

18. The integrated circuit of claim 12 wherein the second component comprises an error checking and correction (ECC) module.

19. The integrated circuit of claim 12 further comprising a third component for determining a one-way function of the output of the second component.

20. A method for repeatedly generating a device-specific value comprising:

in a first component of a device, generating using configurable logic circuitry a first digital value that is substantially dependent on fabrication variation among like devices;

computing redundancy information based on the first digital value;

in the first component of the device, generating using the configurable logic circuitry a subsequent digital value; and

in a second component of the device, determining the first digital value from the subsequent digital value and the redundancy information.

21. The method of claim 20, wherein generating the first digital value comprises generating the first digital value using a lookup table in the configurable logic circuitry.

22. The method of claim 20, wherein the configurable logic circuitry comprises an FPGA.

23. The method of claim 20, wherein the first digital value comprises a device-specific function of an input value inputted to the device.

24. The method of claim 20, wherein the first component comprises a physical unclonable function (PUF) component.

25. The method of claim 20, wherein the second component comprises an error checking and correction (ECC) component.

26. The method of claim 20, wherein the second component comprises a processor implementing an error correction procedure.

27. An integrated circuit comprising:

a first component including configurable logic circuitry configured to generate a digital output value that depends on parameters that vary among like integrated circuits; and

a second component for accepting a digital output value from the first component and accepting redundancy information and determining a corrected output value.

28. The integrated circuit of claim 27, wherein the configurable logic circuitry comprises an FPGA.

29. The integrated circuit of claim 27, wherein the digital output value comprises a device-specific function of an input value inputted to the integrated circuit.

30. The integrated circuit of claim 27, wherein the digital output value of the first component exhibits variation between different instances of providing a digital output.

31. The integrated circuit of claim 27, wherein the digital output value of the first component depends on environmental conditions.

32. The integrated circuit of claim 27, wherein the first component comprises a physical unclonable function (PUF) module.

33. The integrated circuit of claim 27, wherein the second component comprises an error checking and correction (ECC) module.

34. A method for repeatedly generating a device-specific value using redundancy information comprising:

in a first component of a device, generating a first digital value having N=w·

h bits that is substantially dependent on fabrication variation among like devices;

computing redundancy information having R bits based on the first digital value, wherein the redundancy information provides less than N bits of information of the first digital value;

storing the redundancy information, wherein multiple bits of information of the first value are not determinable from the redundancy information;

in the first component of the device, generating a subsequent digital value having N bits;

retrieving the redundancy information;

in a second component of the device, determining the first digital value from the subsequent digital value and the redundancy information by correcting up to h bit differences between the subsequent digital value and the first digital value.

35. The method of claim 34 wherein computing the redundancy information includes computing a part of the redundancy information associated with each of a corresponding different one of h parts of the first digital value.

36. The method of claim 34 wherein further comprising, in the second component of the device, determining if the redundancy information is sufficient to correct all bit differences between the subsequent digital value and the first digital value.