Semiconductor device and methods for making the same

• US 7,691,691 B1
• Filed: 05/23/2007
• Issued: 04/06/2010
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Cleeves, James Montague
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US11/805,620
• Time in Patent Office: 1,049 Days
• Field of Search: 438/163, 438/296, 438/301, 438/305, 438/306, 257/408, 257/E21.413, 257/E29.278
• US Class Current: 438/163
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.

Claims

1. A method for making source/drain tip extensions in a thin film transistor (TFT), comprising the steps of:

a) forming a first dielectric layer adjacent to and in contact with a gate stack and in contact with regions for forming source and drain terminals of the TFT, the gate stack having a gate dielectric layer and a gate electrode, wherein the gate dielectric is between the gate electrode and a channel region of the TFT, and the first dielectric layer has a dopant therein; and

b) heating the first dielectric layer, the gate stack, and the regions for forming source and drain terminals sufficiently to diffuse an amount of the dopant from the first dielectric layer into the channel region effective to form electrically functional source/drain extensions.

2. The method of claim 1, wherein said gate dielectric layer is recessed under the gate.

3. The method of claim 2, further comprising etching said gate dielectric layer to form an undercut space between an outer edge region of the gate and the channel region.

4. The method of claim 3, wherein said first dielectric layer fills the undercut space.

5. The method of claim 3, wherein said undercut space is less than or equal to 10% of the gate length.

6. The method of claim 3, wherein said first dielectric layer fills the undercut space.

7. The method of claim 1, wherein said first dielectric layer has a dielectric constant (k) less than that of the gate dielectric layer.

8. The method of claim 7, wherein the gate dielectric layer is selected from the group consisting of silicon nitride, aluminum oxide, hafnium monoxide and/or hafnium dioxide.

9. The method of claim 7, wherein said first dielectric layer is selected from the group consisting of silicon dioxide doped with boron, silicon dioxide doped with phosphorous, and polyimides.

10. The method of claim 3, wherein said gate dielectric layer is wet etched to form said undercut region.

11. The method of claim 10, wherein said gate comprises a material that is not significantly etched under the wet etching conditions.

12. The method of claim 1, wherein forming said first dielectric layer comprises chemical vapor depositing said first dielectric layer.

13. The method of claim 1, wherein forming said first dielectric layer comprises spin-on depositing a precursor to said first dielectric layer, then converting said precursor to said first dielectric layer.

14. The method of claim 13, wherein said precursor comprises a spin-on glass having wetting characteristics sufficient to form a fillet at the base of the gate.

15. The method of claim 1, wherein said first dielectric layer comprises a lightly doped dielectric layer.

16. The method of claim 15, further comprising forming a heavily doped dielectric layer over or in contact with said lightly doped dielectric layer.

17. The method of claim 1, further comprising removing said first dielectric layer, then forming a heavily doped dielectric layer over or in contact with the gate and the source and drain terminals.

18. A method for making source/drain tip extensions in a thin film transistor (TFT), comprising the steps of:

a) forming a first dielectric layer adjacent to a gate stack and over or in contact with regions for forming source and drain terminals of the TFT, the gate stack having a gate dielectric layer and a gate electrode, wherein the gate dielectric is between the gate electrode and a channel region of the TFT and is recessed under a bottommost surface of the gate electrode, and the first dielectric layer has a dopant therein; and

b) heating the first dielectric layer, the gate stack, and the regions for forming source and drain terminals sufficiently to diffuse an amount of the dopant from the first dielectric layer into the channel region effective to form electrically functional source/drain extensions.

19. The method of claim 18, further comprising etching said gate dielectric layer to form an undercut space between an outer edge region of the gate and the channel region, prior to forming said first dielectric layer.

20. The method of claim 19, wherein said first dielectric layer fills the undercut space.

21. The method of claim 19, wherein said undercut space is less than or equal to 10% of the gate length.

22. The method of claim 19, wherein said gate dielectric layer is wet etched to form said undercut region.

23. The method of claim 22, wherein said gate comprises a material that is not significantly etched under the wet etching conditions.

24. The method of claim 18, wherein forming said first dielectric layer comprises chemical vapor depositing said first dielectric layer.

25. The method of claim 18, wherein forming said first dielectric layer comprises spin-on depositing a precursor to said first dielectric layer, then converting said precursor to said first dielectric layer.

26. The method of claim 25, wherein said precursor comprises a spin-on glass having wetting characteristics sufficient to form a fillet at the base of the gate.

27. The method of claim 18, wherein said first dielectric layer comprises a lightly doped dielectric layer.

28. The method of claim 27, further comprising forming a heavily doped dielectric layer over or in contact with said lightly doped dielectric layer.

29. The method of claim 18, further comprising removing said first dielectric layer, then forming a heavily doped dielectric layer over or in contact with the gate and the source and drain terminals.

30. The method of claim 18, wherein said first dielectric layer has a dielectric constant (k) less than that of the gate dielectric layer.

31. The method of claim 30, wherein the gate dielectric layer is selected from the group consisting of silicon nitride, aluminum oxide, hafnium monoxide and/or hafnium dioxide.

32. The method of claim 30, wherein said first dielectric layer is selected from the group consisting of silicon dioxide doped with boron, silicon dioxide doped with phosphorous, and polyimides.