Semiconductor device including a crystal semiconductor layer, its fabrication and its operation

• US 7,696,032 B2
• Filed: 11/17/2006
• Issued: 04/13/2010
• Est. Priority Date: 11/18/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Min, Yun, Eun-Jung
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US11/561,151
• Publication Number:
  US 20070117344A1
• Time in Patent Office: 1,243 Days
• Field of Search: 438/166, 438/486, 438/489, 438/490, 257/E21.134
• US Class Current: 438/166
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02447 Silicon carbide
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02496 Layer structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET

Abstract

In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

Claims

1. A method of fabricating a semiconductor device comprising:

preparing a semiconductor substrate;

forming a preliminary active pattern on the semiconductor substrate, the preliminary active pattern having a barrier pattern and a non-single crystal semiconductor pattern, which are stacked;

forming a sacrificial non-single crystal semiconductor layer covering the preliminary active pattern and the semiconductor substrate;

crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, thereby changing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern respectively, the crystalline semiconductor pattern and the barrier pattern constituting an active pattern; and

removing the sacrificial crystalline semiconductor layer.

2. The method according to claim 1, wherein the semiconductor substrate comprises a single crystal semiconductor substrate.

3. The method according to claim 1, wherein forming the preliminary active pattern comprises:

sequentially forming a barrier layer and a non-single crystal semiconductor layer on the semiconductor substrate; and

patterning the non-single crystal semiconductor layer and the barrier layer.

4. The method according to claim 1, wherein the preliminary active pattern further comprise a semiconductor pattern underlying the barrier pattern.

5. The method according to claim 4, wherein forming the preliminary active pattern comprises:

sequentially forming a barrier layer and a non-single crystal semiconductor layer on the semiconductor substrate;

patterning the non-single crystal semiconductor layer and the barrier layer to expose a portion of the semiconductor substrate; and

etching the exposed portion of the semiconductor substrate by a particular depth.

6. The method according to claim 1, wherein the barrier pattern comprises an insulating pattern.

7. The method according to claim 6, wherein the insulating pattern comprises a silicon oxide layer, a silicon nitride layer, an oxide/nitride/oxide (ONO) layer, or a high-k dielectric layer.

8. The method according to claim 6, wherein the insulating pattern has a thickness of about 100 Å

or less.

9. The method according to claim 6, which further comprises, after removing the sacrificial crystalline semiconductor layer, forming a gate pattern crossing the active pattern, the gate pattern including a gate insulating layer and a gate electrode, which are sequentially stacked.

10. The method according to claim 9, wherein the insulating pattern is formed thinner than the gate insulating layer.

11. The method according to claim 9, before forming the gate pattern, the method further comprising forming an isolation layer covering the semiconductor substrate around the active pattern.

12. The method according to claim 11, wherein the isolation layer includes a liner insulation layer disposed on sidewalls of the crystalline semiconductor pattern and the semiconductor substrate.

13. The method according to claim 9, further comprising forming a source/drain region inside the active pattern on both sides of the gate pattern.

14. The method according to claim 1, wherein the barrier pattern comprises a metal pattern.

15. The method according to claim 1, wherein the sacrificial crystalline semiconductor layer has an etch selectivity with respect to the crystalline semiconductor pattern.

16. The method according to claim 15, wherein when the crystalline semiconductor pattern comprises silicon, and the sacrificial crystalline semiconductor layer comprises silicon germanium.

17. The method according to claim 1, further comprising:

forming an insulating interlayer over the active pattern, to expose the crystalline semiconductor pattern;

implanting one of n-type or p-type impurity ions into a lower portion of the crystalline semiconductor pattern using the insulating interlayer as an ion implantation mask; and

implanting the other one of n-type or p-type impurity ions into an upper portion of the crystalline semiconductor pattern.

18. The method according to claim 17, further comprising forming a data storage element to be in contact with the crystalline semiconductor pattern.

19. The method according to claim 18, wherein the data storage element includes a phase change material pattern.

20. The method according to claim 18, wherein the data storage element includes a magnetic tunnel junction structure.