Contact pad for thin film transistor substrate and liquid crystal display

• US 7,700,952 B2
• Filed: 04/11/2007
• Issued: 04/20/2010
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Her, Yong Koo, Uh, Kee Han, Park, Yong Han, Shin, Ae
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US11/733,985
• Publication Number:
  US 20070236624A1
• Time in Patent Office: 1,105 Days
• Field of Search: 257/203, 257/208, 257/773, 257/779, 257/59, 257/72, 257/E27.111
• US Class Current: 257/72
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A contact pad is disclosed including a first electrode pattern with an open portion inside, an insulation layer formed on the first electrode pattern and having a contact via portion formed therein, and a second electrode pattern formed on the insulation layer and electrically connected to the first electrode pattern through the contact via portion. The second electrode pattern comprises single electrode patterns spaced apart from one another. A thin film transistor substrate and a liquid crystal display panel having the contact pad are also disclosed.

Claims

1. A thin film transistor substrate, comprising:

a substrate having a display region and a non-display region;

a plurality of gate lines formed in one direction on the substrate;

a plurality of data lines intersecting the plurality of gate lines while being insulated therefrom;

a plurality of single pixels formed at intersections of the plurality of gate and data lines; and

a contact pad formed in the non-display region of the substrate,

wherein the contact pad comprises a first electrode pattern formed in a lattice shape and including a plurality of open portions inside so that the substrate is exposed at the open portions, an insulation layer formed on the first electrode pattern, a plurality of contact vias formed in the insulation layer to be spaced apart from one another and exposing a portion of the first electrode pattern, and a second electrode pattern formed on the insulation layer and including a plurality of single electrode patterns; and

wherein the plurality of single electrode patterns are spaced apart from one another and each of the single electrode patterns is electrically connected to the first electrode pattern though a corresponding contact via,

wherein a conductive contact is positioned above at least a portion of the second electrode pattern.

2. The thin film transistor substrate as claimed in claim 1, wherein each of the single pixels comprises a thin film transistor having gate and source-drain electrodes respectively connected to corresponding gate and data lines, and a pixel electrode connected to the thin film transistor.

3. The thin film transistor substrate as claimed in claim 2, wherein the first electrode pattern is made of the same material as the gate or data line.

4. The thin film transistor substrate as claimed in claim 2, wherein the second electrode pattern is made of the same material as the pixel electrode.

5. A liquid crystal display panel, comprising:

a thin film transistor substrate including a first substrate having a display region and a non-display region, a plurality of single pixels formed on the first substrate to have a plurality of thin film transistors and pixel electrodes, and a contact pad formed in the non-display region of the first substrate;

a color filter substrate including a second substrate, a plurality of color filters formed on the second substrate, and a common electrode formed on the plurality of color filters; and

a conductive contact for electrically connecting the contact pad and the common electrode,

wherein the contact pad comprises a first electrode pattern formed in a lattice shape and including a plurality of open portions inside so that the first substrate is exposed at the open portions, an insulation layer formed on the first electrode pattern, a plurality of contact vias formed in the insulation layer to be spaced apart from one another and exposing a portion of the first electrode pattern, and a second electrode pattern formed on the insulation layer and including a plurality of single electrode patterns; and

wherein the plurality of single electrode patterns are spaced apart from one another and each of the single electrode patterns is electrically connected to the first electrode pattern through a corresponding contact via,

wherein the conductive contact is positioned above at least a portion of the second electrode pattern.

6. The liquid crystal display panel as claimed in claim 5, wherein the conductive contact is formed to be electrically connected to at least a portion of the second electrode pattern.

7. The liquid crystal display panel as claimed in claim 5, wherein the conductive contact is made of a conductive silver paste or a mixture of a resin and a spacer coated with a conductive material.

8. The liquid crystal display panel as claimed in claim 5, wherein the plurality of open portions of the first electrode pattern are spaced apart from one another at a predetermined interval.