System and method for predictive failure detection

• US 7,702,971 B2
• Filed: 06/06/2007
• Issued: 04/20/2010
• Est. Priority Date: 06/06/2007
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Nguyen, Tuyet-Huong T., Khatri, Mukund
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): McMahon; Daniel F
• Application Number:
  US11/759,088
• Publication Number:
  US 20080307273A1
• Time in Patent Office: 1,049 Days
• Field of Search: 714/704, 714/755, 714/805, 714/E11.053, 714/800, 714/751
• US Class Current: 714/704
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.

Claims

1. A method of predicting failure of an information handling system, comprising:

determining an error period;

determining that an error has occurred;

incrementing an error count;

if the error is the first error of the error count, waiting until a next error;

if the error is not the first error of the error count, such that there is a previous error determining a time difference between the error and the previous error;

if the time difference is less than the error period, generating data representing a predicted failure;

if the time difference is greater than the error period, calculating the product of the error period and the error count;

if the time difference is greater than the product of the error period and the error count, clearing the error count;

if the time difference is less than the product of the error period and the error count, decrementing the error count by a leak value representing the time difference divided by the error period; and

repeating the above steps for each new error.

2. The method of claim 1, wherein the error is a correctable error.

3. The method of claim 1, wherein the method is performed by BIOS of the information handling system.

4. The method of claim 3, wherein the step of determining that an error has occurred is performed by receiving an interrupt signal.

5. The method of claim 1, wherein the method is performed by an operating system.

6. The method of claim 1, wherein the method is performed by a service processor.

7. The method of claim 1, wherein the errors are a type from the group of error types:

ECC errors or CRC errors.

8. The method of claim 1, wherein the errors are a type from the following error types:

memory errors, bus errors, and CPU cache errors.

9. A computer-readable medium having computer-executable instructions that when executed predict failure of an information handling system, comprising:

instructions that when executed perform the following operations;

determining an error period;

determining that an error has occurred;

incrementing an error count;

if the error is the first error of the error count, waiting until a next error;

if the error is not the first error of the error count, such that there is a previous error, determining a time difference between the error and the previous error;

if the time difference is less than the error period, generating data representing a predicted failure;

if the time difference is greater than the error period, determining calculating the product of the error period and the error count;

if the time difference is greater than the product of the error period and the error count, clearing the error count;

if the time difference is less than the product of the error period and the error count, decrementing the error count by a leak value representing the time difference divided by the error period; and

repeating the above steps for each new error.

10. The computer-readable medium of claim 9, wherein the error is a correctable error.

11. The computer-readable medium of claim 9, wherein the method is performed by BIOS of the information handling system.

12. The computer-readable medium of claim 11, wherein the step of determining that an error has occurred is performed by receiving an interrupt signal.

13. The computer readable medium of claim 9, wherein the computer readable medium is part of an operating system.

14. The computer readable medium of claim 9, wherein the computer readable medium is implemented with a service processor.

15. The computer-readable medium of claim 9, wherein the errors are a type from the group of error types:

ECC errors or CRC errors.

16. The computer-readable medium of claim 9, wherein the errors are a type from the following error types:

memory errors, bus errors, and CPU cache errors.