Memory with level shifting word line driver and method thereof

• US 7,706,207 B2
• Filed: 09/12/2008
• Issued: 04/27/2010
• Est. Priority Date: 05/15/2006
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pelley, III, Perry H., Liston, Thomas W., Chowdhury-Nagle, Shahnaz P.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US12/209,477
• Publication Number:
  US 20090021990A1
• Time in Patent Office: 592 Days
• Field of Search: 365/230.06, 365/63, 365/189.11
• US Class Current: 365/230.03
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Claims

1. A circuit device comprising:

a word line driver having a first input to receive a first predecode value, a second input to receive a second predecode value, and an output coupled to a word line of a memory, the word line driver comprising;

a first transistor having a gate electrode coupled to the first input, a first current electrode coupled to the second input, and a second current electrode coupled to a first node;

a second transistor having a gate electrode coupled to a first voltage reference, a first current electrode coupled to a second voltage reference, and a second current electrode coupled to the first node;

a third transistor having a gate electrode coupled to the first node, a first current electrode coupled to a third voltage reference, and a second current electrode coupled to a second node;

a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node, and a second current electrode coupled to the first voltage reference; and

wherein the second node is coupled to the word line.

2. The circuit device of claim 1, wherein the first transistor and fourth transistor comprise n-channel transistors.

3. The circuit device of claim 2, wherein the second transistor and third transistor comprise p-channel transistors.

4. The circuit device of claim 1, further comprising:

address decode circuitry having a first output coupled to the first input of the word line driver to provide the first predecode value and a second output coupled to the second input of the word line driver to provide the second predecode value.

5. The circuit device of claim 4, wherein the address decode circuitry comprises transistors having a first gate oxide thickness and the first transistor, the second transistor, third transistor and fourth transistor have a second gate oxide thickness greater than the first gate oxide thickness.

6. The circuit device of claim 5, wherein the address decode circuitry is operable at a first voltage and the word line driver is operable at a second voltage greater than the first voltage.

7. The circuit device of claim 6, wherein the first voltage is approximately 0.9 volts and the second voltage is approximately 1.2 volts.

8. The circuit device of claim 1, wherein the second voltage reference is substantially equal to the third voltage reference.

9. A memory comprising:

a plurality of global word lines;

global word line driver circuitry having a plurality of outputs, each output coupled to a corresponding global word line of the plurality of global word lines;

address decode circuitry having an output to provide a predecode value;

a local bit cell array comprising a plurality of local word lines;

local word line driver circuitry having an input coupled to the output of the address decode circuitry, an input coupled to a corresponding global word line of the plurality of global word lines, and a plurality of outputs, each output coupled to a corresponding local word line of the plurality of local word lines, wherein the local word line driver circuitry comprises a plurality of voltage level shifters, each voltage level shifter associated with a corresponding local word line of the local bit cell array;

wherein the global word line driver circuitry and address decode circuitry are operable in a first voltage domain; and

wherein the local bit cell array and local word line driver circuitry are operable in a second voltage domain different than the first voltage domain.

10. The memory of claim 9, wherein each voltage level shifter of the local word line driver circuitry comprises:

a first transistor having a gate electrode coupled to receive one of a corresponding bit value of the predecode value or a value at the corresponding global word line, a first current electrode coupled to receive the other of the corresponding bit value of the predecode value or the value at the corresponding global word line, and a second current electrode coupled to a first node;

a second transistor having a gate electrode coupled to a first voltage reference, a first current electrode coupled to a second voltage reference, and a second current electrode coupled to the first node;

a third transistor having a gate electrode coupled to the first node, a first current electrode coupled to a third voltage reference, and a second current electrode coupled to a second node;

a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node, and a second current electrode coupled to the first voltage reference; and

wherein the second node is coupled to the corresponding local word line.

11. The memory of claim 10, wherein the second voltage reference is substantially equal to the third voltage reference.

12. The memory of claim 10, wherein:

the global word line driver circuitry and the address decode circuitry comprise transistors having a first gate oxide thickness; and

the local bit cell array and local word line driver circuitry comprise transistors having a second gate oxide thickness different than the first gate oxide thickness.

13. The memory of claim 12, wherein the first gate oxide thickness is less than 14 angstroms and wherein the second gate oxide thickness is less than 19 angstroms.