System for using test structures to evaluate a fabrication of a wafer

• US 7,723,724 B2
• Filed: 08/21/2008
• Issued: 05/25/2010
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Vickers, James S., Estabil, Jose J.
• Primary Examiner(s): Tran; Long K
• Application Number:
  US12/196,032
• Publication Number:
  US 20080315196A1
• Time in Patent Office: 642 Days
• Field of Search: 438/11, 438/14, 438/15, 438/18, 257/48, 257/E23.179, 257/E21.521, 257/E21.524, 430/30, 324/751, 324/765
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system is provided for using test structures to evaluate a fabrication of a wafer. The test structures include a combination of device and interconnect elements that are provided on an active region of a die, on the wafer prior to the fabrication of the wafer being completed. The combination of device and interconnect elements include one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics. A power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer. The one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits. A detector is provided to detect the output over the contactless medium, so as to receive the output without affecting a usability of the wafer when fabrication is completed.

Claims

1. A system for evaluating a fabrication of a wafer that includes one or more die, the system comprising:

one or more test structures that each comprise;

a combination of device and interconnect elements that are provided on an active region of a die on the wafer prior to the fabrication of the wafer being completed, the combination of device and interconnect elements including one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics;

includes a power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium;

wherein the one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits;

a detector to detect the output over the contactless medium, so as to receive the output without affecting a usability of the wafer when fabrication is completed.

2. The system of claim 1, wherein the output of one or more of the plurality of test structures includes at least one of an electrostatic, electromagnetic, or inductive signal that is created by an output of each of the one or more test structures in response to being triggered.

3. The system of claim 1, wherein the output of one or more of the plurality of test structures is a radio-frequency output that has a characteristic that identifies the test structure from other test structures.

4. The system of claim 1, wherein the of device and interconnect elements of one or more of the plurality of test structures includes a plurality of transistors.

5. The system of claim 1, wherein the plurality of test structures are configured to be concurrently.

6. The system of claim 5, wherein the output from at least some of the plurality of test structures identify those test structures from other test structures on the wafer.

7. The system of claim 1, wherein each of the plurality of test structures are at least partially tiggerable by a common energy beam.

8. The system of claim 7, wherein the electrical activity of one or more of the plurality of test structures includes photons produced from a switch element in the combination of device and interconnect elements of the one or more test structures.

9. The system of claim 1, wherein the of device and interconnect elements of one or more of the plurality of test structures includes a plurality of interconnected inverters.

10. The system of claim 9, wherein the of device and interconnect elements of one or more of the plurality of test structures includes one or more CMOS inverters.