Leakage current cancellation for integrated analog switch
First Claim
1. An integrated analog switch, comprising:
- a first semiconductor device having first and second current terminals, a control terminal and a body, wherein said first and second current terminals are coupled to first and second switch terminals, respectively;
wherein said first semiconductor device, when turned off, causes a first leakage current between said body of said first semiconductor device and said first switch terminal;
a second semiconductor device comprising first and second current terminals, a control terminal and a body, wherein said first current terminal of said second semiconductor device is coupled to said first switch terminal and wherein said second current terminal of said second semiconductor device is coupled to said body of said first semiconductor device;
wherein said second semiconductor device, when turned off, causes a second leakage current between said body of said second semiconductor device and said first switch terminal, wherein said second leakage current is proportional to said first leakage current; and
a first current mirror circuit, coupled to said first switch terminal and to said body of said second semiconductor device, which mirrors and amplifies said second leakage current to provide a first cancellation current which is applied to said first switch terminal, wherein said first cancellation current is equivalent to a sum of said first and second leakage currents.
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Abstract
An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.
42 Citations
21 Claims
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1. An integrated analog switch, comprising:
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a first semiconductor device having first and second current terminals, a control terminal and a body, wherein said first and second current terminals are coupled to first and second switch terminals, respectively; wherein said first semiconductor device, when turned off, causes a first leakage current between said body of said first semiconductor device and said first switch terminal; a second semiconductor device comprising first and second current terminals, a control terminal and a body, wherein said first current terminal of said second semiconductor device is coupled to said first switch terminal and wherein said second current terminal of said second semiconductor device is coupled to said body of said first semiconductor device; wherein said second semiconductor device, when turned off, causes a second leakage current between said body of said second semiconductor device and said first switch terminal, wherein said second leakage current is proportional to said first leakage current; and a first current mirror circuit, coupled to said first switch terminal and to said body of said second semiconductor device, which mirrors and amplifies said second leakage current to provide a first cancellation current which is applied to said first switch terminal, wherein said first cancellation current is equivalent to a sum of said first and second leakage currents. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated MOS switch, comprising:
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a first MOS device having first and second current terminals coupled to first and second switch terminals, respectively, a control terminal receiving a first switch control signal, and a body, wherein said first MOS device provides a first leakage current between said body and said first switch terminal and a second leakage current between said body and said second switch terminal when said first MOS device is turned off by said first switch control signal; a second MOS device having a first current terminal coupled to said first switch terminal, a second current terminal coupled to said body of said first MOS device, a control terminal receiving said first switch control signal, and a body, wherein said second MOS device provides a third leakage current between said body and said first switch terminal when said second MOS device is turned off by said first switch control signal; a third MOS device having a first current terminal coupled to said second switch terminal, a second current terminal coupled to said body of said first MOS device, a control terminal receiving said first switch control signal, and a body, wherein said third MOS device provides a fourth leakage current between said body and said second switch terminal when said third MOS device is turned off by said first switch control signal; a first hold circuit which holds said body of said first MOS device to a first voltage when said first MOS device is turned off by said first switch control signal; a first mirror circuit which holds said body of said second MOS device to said first voltage when said second MOS device is turned off by said first switch control signal, and which applies a first cancellation current to said first switch terminal to cancel said first and third leakage currents based on mirroring and amplifying said third leakage current; and a second mirror circuit which holds said body of said third MOS device to said first voltage when said third MOS device is turned off by said first switch control signal, and which applies a second cancellation current to said second switch terminal to cancel said second and fourth leakage currents based on mirroring and amplifying said fourth leakage current. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of canceling a leakage current of an integrated analog switch, wherein the integrated analog switch comprises a first semiconductor device having first and second current terminals coupled to first and second switch terminals, respectively, a body and a control terminal receiving a switch control signal, wherein the leakage current is developed through the body and the first current terminal when the first semiconductor switch device is turned off and when the body is pulled to a bias voltage level, said method comprising:
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providing a second semiconductor device being a reduced-size replica of the first semiconductor device, wherein the second semiconductor device has first and second current terminals, a control terminal and a body; providing the switch control signal to the control terminal of the second semiconductor device; coupling the first current terminal of the second semiconductor device to the first current terminal of the first semiconductor device and coupling the second current terminal of the second semiconductor device to the body of the first semiconductor device; pulling the body of the second semiconductor device to the bias voltage level when the first and second semiconductor devices are both turned off by the switch control signal, wherein the second semiconductor device develops a proportional current between the first current terminal and body of the second semiconductor device and wherein the proportional current is proportional to the leakage current of the first semiconductor device; mirroring and amplifying the proportional current to provide a cancellation current; and applying the cancellation current to the first switch terminal. - View Dependent Claims (20, 21)
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Specification