Contactless technique for evaluating a fabrication of a wafer

• US 7,730,434 B2
• Filed: 08/25/2004
• Issued: 06/01/2010
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Estabil, Jose J.
• Primary Examiner(s): Do; Thuan
• Assistant Examiner(s): Doan; Nghia M
• Application Number:
  US10/927,275
• Publication Number:
  US 20050085932A1
• Time in Patent Office: 2,106 Days
• Field of Search: 716 4- 5, 702/57, 702/118, 702/127, 702/134, 702/172, 438 14- 18, 257/E21.524, 324/537, 324/750, 324752-753, 324/765
• US Class Current: 716/136
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A method for evaluating manufacturing of a product wafer, the method comprising the steps of:

measuring an electrical activity from multiple activated circuits located at a plurality of locations on an active area of a die of the wafer, wherein the wafer is in a partially completed state;

wherein measuring the electrical activity includes directly measuring the electrical activity using the off-wafer probe so as to associate the electrical activity as measured from each of the activated circuits with a corresponding one of the plurality of locations where that activated circuit is located;

determining performance-related information of the die or wafer by relating one or more physical or electrical characteristics of at least the portion of the wafer to data corresponding to the measured electrical activity;

wherein the step of measuring the electrical activity is performed without physically contacting the active area of the die of the wafer, and without affecting subsequent manufacturing of the wafer into final product form after measuring the electrical activity; and

wherein determining performance-related information includes (i) determining values of a performance parameter from the measured electrical activity of activated circuits at the plurality of the locations, and (ii) determining variance from the determined values of the performance parameter.

2. The method of claim 1, wherein determining performance-related information includes determining a spatial variance from the determined values of the performance parameter.

3. The method of claim 1, wherein determining performance-related information includes determining a variance of switching characteristics from the determined values of the performance parameter.

4. The method of claim 1, further comprising correlating the variance in the determined values of the performance parameter to one or more corresponding processes in the manufacturing of the wafer.

5. The method of claim 4, further comprising the step of evaluating how one or more corresponding processes in the manufacturing are performed using the variance in the determined values of the performance parameter.

6. The method of claim 4, further comprising the step of correlating the variance determined from the value of the performance parameter to an electrical or physical attribute of a device on the die;

wherein the attribute is a result of one or more corresponding steps in the manufacturing of the wafer.

7. The method of claim 6, wherein the step of correlating the variance determined from the values of the performance parameter to an attribute of a device on the die includes correlating the variance to a gate length or gate width variation of multiple switching elements on the die;

wherein the gate length or gate width variation is a result of one or more corresponding variations in performance of one or more steps in the manufacturing of the wafer.

8. The method of claim 6, wherein the step of correlating the variance determined from the value of the performance parameter to the electrical or physical attribute of the device on the die includes correlating the variance determined from the values of the performance parameter to a capacitance characteristic on any portion of the die;

wherein the capacitance characteristic is a result of performance of one or more steps in the manufacturing of the wafer.

9. The method of claim 6, wherein the step of correlating the variance determined from the values of the performance parameter to the electrical or physical attribute of the device on the die includes correlating the variance determined from the values of the performance parameter to a resistance characteristic on any portion of the die;

wherein the resistance characteristic results from performance of one or more steps in the manufacturing of the wafer.

10. The method of claim 6, wherein the step of correlating the variance determined from the values of the performance parameter to the electrical or physical attribute of the device on the die includes correlating the variance determined from the values of the performance parameter to an electrical bias characteristic on any portion of the die, wherein the electrical bias characteristic results from the manufacturing of the wafer.

11. The method of claim 6, wherein the attribute is a result performance of one or more steps for etching the wafer, including wafer planarization.

12. The method of claim 10, wherein the attribute is a result of performance one or more steps for a patterning process, including one or both of lithography or etching.

13. The method of claim 6, wherein the step of correlating the variance determined from the value of the performance parameter to the electrical or physical attribute of the device on the die includes correlating the variance determined from the values of the performance parameter to a resistivity variation of any one or more switching elements on the die;

wherein the resistivity variation is a result of performance of one or more steps in the manufacturing of the wafer.

14. The method of claim 4, further comprising the step of adjusting how the one or more steps in the manufacturing of the wafer are performed using the measured variation.

15. The method of claim 4, further comprising correlating the variance to a specific manufacturing step or sequence.

16. The method of claim 1, wherein the step of determining performance-related information includes isolating one or more steps in the manufacturing of the wafer as attributing to the variance of the values of the performance parameter.

17. The method of claim 1, wherein the step of measuring the electrical activity includes measuring, from one of the plurality of circuit elements disposed at each of the plurality of locations on the die, at least one of (i) a switching speed, (ii) circuit delay and (iii) slew rate.

18. The method of claim 1, using the variance to evaluate how one or more processes in the manufacturing are performed from a set of processes consisting of:

a lithography process, an etch process, a deposition process, a polishing process, and an interconnectivity process.

19. The method of claim 1, wherein measuring the electrical activity is performed using activated circuits that are formed as a result of one or more fabrication steps that achieve first electrical connectivity and circuit functionality.

20. The method of claim 1, wherein measuring an electrical activity includes detecting signals originating from the individual locations without use of a transmission pad or antenna.

21. An apparatus comprising a computer readable storage device, wherein the computer readable storage device stores instructions for evaluating manufacturing of a product wafer, wherein at least some of the instructions are executable to enable the apparatus to:

determine, at a plurality of locations on an active area of a die in the product wafer, a value of a specified performance parameter, wherein the specified performance parameter is known to be indicative of a result of one or more fabrication steps in the fabrication;

wherein the value of the specified performance parameter is determined by attributing an electrical activity directly measured from each of a plurality of activated circuits with a corresponding location of that activated circuit without physically contacting or altering the active areas of the die, so as to not affect usability of the product wafer when completed;

determine a variance in the values of the specified performance parameter from the measured electrical activity at the plurality of locations; and

obtain evaluation information based on the variance of the value of the performance parameter, wherein the evaluation information enables evaluation of how the one or more fabrication steps were performed.

22. A method for evaluating the manufacturing of a product wafer, the method comprising:

measuring, using an off-wafer probe, an electrical activity from multiple activated circuits located at a plurality of locations on an active area of a die of the product wafer, wherein the wafer is in a partially completed state;

wherein measuring the electrical activity includes directly measuring the electrical activity using the off wafer probe so as to associate the electrical activity as measured from each of the activated circuits with a corresponding one of the plurality of locations where that activated circuit is located;

wherein measuring the electrical activity is performed without contacting the wafer and without affecting completion of manufacturing the wafer into product form;

obtaining a value of a performance parameter at the plurality of locations, the value of the performance parameter at each of the plurality of locations being based on the directly measured electrical activity of one or more activated circuits at the corresponding location of each of the one or more activated circuits; and

evaluating one or more physical or electrical characteristics of at least the portion of the wafer in the partially completed state by analyzing the values of the performance parameter at the plurality of locations;

wherein analyzing the values of the performance parameter includes determining variance in the values of performance parameter that are obtained from activated circuits located at different locations of the wafer that include the active area.

23. The method of claim 22, wherein obtaining a value of a performance parameter includes measuring the electrical activity at one or more activated circuits in die of the wafer.

24. The method of claim 23, wherein measuring the electrical activity is performed as a function of a measurement tool or measurement technique.

25. The method of claim 23, wherein measuring an electrical activity includes inducing the electrical activity and then measuring the electrical activity without contacting the wafer.

26. The method of claim 23, wherein measuring an electrical activity includes measuring an optoelectronic or photonic effect from one or more of the activated circuits at the plurality of locations.

27. The method of claim 26, wherein the optoelectronic or photonic effect of one or more of the activated circuits at one or more of the plurality of locations is provided by at least one of an ion beam, an e-beam, or a hot-electron photon emission.

28. The method of claim 23, wherein measuring an electrical activity includes measuring a radio-frequency signal generated from one or more of the activated circuits at the plurality of locations.

29. The method of claim 23, measuring an electrical activity includes measuring a voltage variation of one or more activated circuits at one or more of the plurality of locations.

30. The method of claim 22, wherein obtaining a value of a performance parameter includes obtaining the values of the performance parameter that correspond to a measurement of one of a timing measurement or a slew rate measurement made at one or more of the plurality of locations.

31. The method of claim 30, wherein the timing measurement corresponds to the measurement of one of (i) a frequency of an electrical signal of one or more activated circuits at one or more of the plurality of locations, or (ii) a timing or phase delay across an electrical element at one or more activated circuits at each of the plurality of locations.

32. The method of claim 22, wherein obtaining a value of a performance parameter includes calculating one or more values of the performance parameter by measuring the electrical activity from one or more activated circuits at one or more designated locations in die of the wafer.

33. The method of claim 22, wherein the measuring the electrical activity includes measuring the electrical activity that corresponds to one or more of (i) a timing or phase delay amongst electrical elements on the portion of the wafer, (ii) a frequency of operation of electrical elements on the portion of the wafer, or (iii) a determination of gate switching speed.

34. The method of claim 22, wherein analyzing the values of the performance parameter at the plurality of locations is performed when the wafer is in the partially completed state.

35. The method of claim 22, wherein determining the variance of includes comparing the variance to one or more expected values for when the wafer is in the partially completed state.

36. The method of claim 22, further comprising designing one or more aspects of at least the portion of the wafer, and wherein the step of evaluating the one or more physical or electrical characteristics is performed as part of designing the one or more aspects.

37. The method of claim 36, wherein designing one or more aspects of at least the portion of the wafer includes designing a layout of one or more elements on at least the portion of the wafer, wherein the one or more physical or electrical characteristics are characteristic of the layout, and wherein evaluating one or more physical or electrical characteristics includes using the value of the performance parameters measured from one or more activated circuits at one or more of the plurality of locations to determine whether the one or more physical or electrical characteristics for the layout satisfy a requirement for the fabrication of the wafer.

38. The method of claim 37, wherein designing one or more aspects of at least the portion of the wafer includes simulating one or more elements of the portion of the wafer when the wafer is in the partially completed state, and wherein evaluating the one or more physical or electrical characteristics includes comparing a result indicated by the performance parameters measured from one or more of the activated circuits at each of the plurality of locations to one or more expected results from simulating the one or more elements.

39. The method of claim 22, wherein analyzing the values of the performance parameter at each of the plurality of locations includes using the value of the performance parameter at one or more of the plurality of locations to determine, for the wafer in the partially completed state, a characterization of one or more of a physical characteristic, a material characteristic or an electrical characteristic.

40. The method of claim 39, wherein analyzing the value of the performance parameter at each of the plurality of locations includes comparing the characterization to an expected result of one or more manufacturing processing steps that be performed.

41. The method of claim 22, further comprising monitoring a portion of the fabrication using information from evaluating the one or physical or electrical characteristics.

42. The method of claim 41, further comprising adjusting performance of one or more processing steps in the fabrication based at least in part on information determined from evaluating the one or more physical or electrical characteristics.

43. The method of claim 41, wherein monitoring the portion of the fabrication includes using information that corresponds to the variance.

44. The method of claim 22, further comprising designing one or more aspects of at least the portion of the wafer, and wherein the step of evaluating the one or more physical or electrical characteristics is performed as part of designing the one or more aspects.

45. The method of claim 44, wherein designing one or more aspects of at least the portion of the wafer includes designing a layout of one or more elements on at least the portion of the wafer, wherein the one or more physical or electrical characteristics are characteristic of the layout, and wherein evaluating one or more physical or electrical characteristics includes using the values of the performance parameters measured at the plurality of locations to determine whether the one or more physical or electrical characteristics for the layout satisfy a requirement for the fabrication of the wafer.

46. The method of claim 44, wherein designing one or more aspects of at least the portion of the wafer includes simulating one or more elements of the portion of the wafer when the wafer is in the partially completed state, and wherein evaluating the one or more physical or electrical characteristics includes comparing a result indicated by the performance parameter measured from one or more activated circuits at the plurality of locations to one or more expected results from simulating the one or more elements.

47. The method of claim 22, wherein analyzing the values of the performance parameter at each of the plurality of locations includes using the values of the performance parameter at one or more of the plurality of locations to determine, for the wafer in the partially completed state, a characterization of one or more of a physical characteristic, a material characteristic or an electrical characteristic.

48. The method of claim 47, wherein analyzing the values of the performance parameter at each of the plurality of locations includes comparing the characterization to an expected result of one or more manufacturing processing steps that be performed.

49. The method of claim 22, further comprising monitoring a portion of the fabrication using information from evaluating the one or physical or electrical characteristics.

50. The method of claim 49, wherein monitoring the portion of the fabrication includes determining the variance of the value of a specific class of performance parameters at multiple locations on the wafer.

51. The method of claim 50, wherein monitoring the portion of the fabrication includes:

correlating the variance to one or more specific processing steps required to complete manufacturing of the wafer, the one or more specific manufacturing processing steps excluding one or more other manufacturing processing steps required to complete the fabrication of the wafer, and wherein the one or more physical or electrical characteristics result from, or are affected by, the specific one or more manufacturing processing steps.

52. The method of claim 49, wherein monitoring the portion of the fabrication includes monitoring performance of one or more of a lithography process, an etch process, a deposition process, a polishing process, or a gate formation and interconnectivity process.

53. The method of claim 22, further comprising adjusting performance of one or more processing steps in the fabrication based at least in part on information determined from evaluating the one or more physical or electrical characteristics, including the determined variance.

54. The method of claim 53,

wherein adjusting performance of one or more manufacturing processing steps further comprises adjusting performance of at least a portion of the manufacturing processing steps performed in the fabrication based at least in part on correlating the variance to the one or more physical or electrical characteristics.

55. The method of claim 22, wherein evaluating one or more physical or electrical characteristics of at least the portion of the wafer includes performing statistical analysis in determining the variance.

56. The method of claim 22, wherein measuring the electrical activity is performed using activated circuits that are formed as a result of one or more fabrication steps that achieve first electrical connectivity and circuit functionality.

57. The method of claim 22, wherein measuring an electrical activity includes detecting signals originating from the individual locations without use of a transmission pad or antenna.