Method for depositing a diffusion barrier for copper interconnect applications

• US 7,732,314 B1
• Filed: 03/05/2007
• Issued: 06/08/2010
• Est. Priority Date: 03/13/2001
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Original Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Inventors: Danek, Michal, Rozbicki, Robert
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US11/714,465
• Time in Patent Office: 1,191 Days
• Field of Search: None
• US Class Current: 438/584
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence

Abstract

Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

Claims

1. A method for depositing a diffusion barrier and a metal conductive layer on a wafer substrate, the method comprising:

(a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;

(b) etching through at least part of the first portion of the diffusion barrier at bottom portions of a plurality of vias to expose at least part of an underlying metal layer, while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the wafer substrate, wherein the etching comprises removing the diffusion barrier material by impinging on the substrate with energetic inert gas ions;

(c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and

(d) depositing the metal conductive layer over the surface of the wafer substrate, such that the metal conductive layer is deposited on the third portion of the diffusion barrier at least at the bottom portions of the plurality of vias.

2. The method of claim 1, wherein (b) comprises sputtering metal from a negatively biased metal target in a PVD process chamber resulting in net deposition at least in the field region.

3. The method of claim 1, wherein the substrate comprises a plurality of unlanded vias.

4. The method of claim 1, further comprising etching the third portion of diffusion barrier at least at the bottom portions of the vias without fully etching through such that an amount of the metal-containing material remains at the bottoms of the vias prior to (d).

5. The method of claim 1, wherein (b) comprises removing contaminants from a top portion of the underlying metal layer, while simultaneously depositing the second portion of the diffusion barrier material at least on the field region.

6. The method of claim 1, wherein in (b) an etch rate to deposition rate ratio is less than 1 at a bottom portion of a trench.

7. A method for depositing a diffusion barrier and a metal conductive layer on a wafer substrate comprising a plurality of unlanded vias, the method comprising:

(a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;

(b) etching through at least part of the first portion of the diffusion barrier at the bottoms of the plurality of unlanded vias to expose at least part of an underlying metal layer and a dielectric layer, while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the wafer substrate;

(c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and

(d) depositing the metal conductive layer over the surface of the wafer substrate, such that the metal conductive layer is deposited on the third portion of the diffusion barrier at least at the bottom portions of the plurality of vias.

8. The method of claim 7, wherein (b) comprises sputtering metal from a negatively biased metal target in a PVD process chamber resulting in net deposition at least in the field region.

9. The method of claim 8, wherein in (b) the etching comprises removing the diffusion barrier material by impinging on the substrate with energetic inert gas ions.

10. The method of claim 7, further comprising etching the third portion of diffusion barrier at least at the bottom portions of the vias without fully etching through such that an amount of the metal-containing material remains at the bottoms of the vias prior to (d).

11. The method of claim 7, wherein (b) comprises removing contaminants from a top portion of the underlying metal layer, while simultaneously depositing the second portion of the diffusion barrier material at least on the field region.

12. The method of claim 7, wherein in (b) an etch rate to deposition rate ratio is less than 1 at a bottom portion of a trench.

13. The method of claim 7, further comprising heating the wafer to between about 200 to 400°

C. prior to (a) to remove unwanted moisture.

14. The method of claim 7, wherein method does not employ a precleaning operation prior to (a).

15. The method of claim 7, wherein at least two successive operations in (a) through (c) are performed in the same processing chamber.

16. The method of claim 15, wherein the processing chamber comprises a hollow cathode magnetron.

17. The method of claim 7, wherein the diffusion barrier layer deposited in (a) comprises a material selected from the group consisting of W, Ti, and Ta nitrides, and wherein the metal conductive layer deposited in (d) comprises Cu.

18. The method of claim 1, wherein the diffusion barrier layer deposited in (a) comprises a material selected from the group consisting of W, Ti, and Ta nitrides, and wherein the metal conductive layer deposited in (d) comprises Cu.

19. The method of claim 1, further comprising heating the wafer to between about 200 to 400°

C. prior to (a) to remove unwanted moisture.

20. The method of claim 7, wherein at least two successive operations in (a) through (c) are performed in the same processing chamber comprising a hollow cathode magnetron.