Oscillator devices and methods thereof

• US 7,733,191 B2
• Filed: 02/28/2007
• Issued: 06/08/2010
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Olmos, Alfredo, Soldera, Jefferson Daniel De Barros, Berens, Michael Todd, Qian, Gang
• Primary Examiner(s): Tan, Vibol
• Assistant Examiner(s): Tran, Jany
• Application Number:
  US11/680,218
• Publication Number:
  US 20080204155A1
• Time in Patent Office: 1,196 Days
• Field of Search: 331/34, 331/108.R, 331/111, 331/143, 331/176, 331/177.R
• US Class Current: 331/111
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

Oscillator devices and methods of operating such oscillator devices are disclosed. The oscillator devices include a current source, and an oscillation module to provide a clock signal. The frequency of the clock signal depends on the relationship between a threshold voltage of a transistor at the oscillation module and the current level provided by the current source. The transistor at the oscillation module is matched to a transistor at the current source so that the frequency of the clock signal is relatively insensitive to changes in device temperature.

Claims

1. A method comprising:

applying a first current to charge a capacitor to a first voltage level during a first interval, the first voltage level dependent on a first threshold voltage;

generating a first clock signal interval in response to the capacitor charge reaching the first threshold voltage;

reversing a polarity of the capacitor in response to the capacitor charge reaching the first threshold voltage during the first interval;

applying the first current to charge the capacitor to a second voltage level during a second interval, the second voltage level dependent on a second threshold voltage; and

generating a second clock signal interval in response to the capacitor charge reaching the second threshold voltage.

2. The method of claim 1, wherein generating the first clock signal comprises:

asserting a first signal based on a charge of the capacitor;

applying the first signal to a first input of a flip-flop;

asserting a second signal based on the charge of the capacitor; and

applying the second signal to a second input of the flip-flop.

3. The method of claim 1, wherein generating the first clock signal comprises providing a first current to a first inverter in response to the capacitor charge reaching the first threshold voltage.

4. The method of claim 3, further comprising providing an inverted representation of a signal from the first inverter to an input of a latch.

5. The method of claim 4, wherein the latch comprises a set-reset flip flop.

6. The method of claim 5, wherein generating the first clock signal comprises providing a second current to a second inverter in response to switching the polarity of the capacitor.

7. The method of claim 1, further comprising reversing the polarity of the capacitor in response to the capacitor charge reaching the second threshold voltage during the second interval.

8. A device, comprising

a current source comprising:

a first transistor comprising a first current electrode coupled to a first voltage reference, a second current electrode coupled to a second voltage reference, and a control electrode coupled to the second voltage reference;

a second transistor comprising a first current electrode coupled to the first voltage reference, a second current electrode coupled to the control electrode of the first transistor, and a control electrode coupled to the first current electrode of the first transistor; and

an output coupled to the first current electrode of the first transistor;

a switching module comprising;

a capacitor comprising a first current electrode responsive to a voltage at the output of the current source during a first interval and a second current electrode responsive to a voltage at the output of the current source during a second interval; and

a first control module comprising a third transistor that is matched with the first transistor, the third transistor comprising a first current electrode coupled to the first voltage reference, a second current electrode coupled to the second voltage reference, and a control electrode coupled to the first current electrode of the capacitor;

a second control module comprising a fourth transistor that is matched with the first transistor, the fourth transistor comprising a first current electrode coupled to the first voltage reference, a second current electrode coupled to the second voltage reference, and a control electrode coupled to the second current electrode of the capacitor; and

a latch comprising a first input coupled to the first current electrode of the third transistor, a second input coupled to the first current electrode of the fourth transistor, and a first output configured to provide a periodic signal based on a first signal at the first input and a second signal at the second input.

9. The device of claim 8, wherein the switching module further comprises:

a fifth transistor comprising a first current electrode coupled to the first voltage reference, a second current electrode coupled to the second current electrode of the capacitor, and a control electrode coupled to a second output of the latch; and

a sixth transistor comprising a first current electrode coupled to the first voltage reference, a second current electrode coupled to the first current electrode of the capacitor, and a control electrode coupled to the first output of the latch.

10. The device of claim 9, wherein the switching module further comprises:

a seventh transistor comprising a first current electrode coupled to the second current electrode of the capacitor, a second current electrode coupled to the second voltage reference, and a control electrode coupled to the second output of the latch; and

an eighth transistor comprising a first current electrode coupled to the first current electrode of the capacitor, a second current electrode coupled to the second voltage reference, and a control electrode coupled to the first output of the latch.

11. The device of claim 8, wherein the latch is a set-reset flip flop.

12. The device of claim 8 further comprising a plurality of resistors coupled in series between the second current electrode of the second transistor and the second voltage reference.

13. The device of claim 12 wherein a first of the plurality of resistors comprises a N doped poly resistor and a second of the plurality of resistors is a P doped poly resistor.

14. The device of claim 8, wherein the first, second and third transistors are CMOS transistors.