System and apparatus for using test structures inside of a chip during the fabrication of the chip

• US 7,736,916 B2
• Filed: 06/14/2007
• Issued: 06/15/2010
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Vickers, James S., Estabil, Jose J.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US11/762,944
• Publication Number:
  US 20070238206A1
• Time in Patent Office: 1,097 Days
• Field of Search: 438/11, 438/E21.525
• US Class Current: 438/11
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:

identifying a location on a die of the wafer for each of a plurality of test structures;

when the wafer is in a partially fabricated form, generating a corresponding signal from each of the plurality of test structures by directing energy onto the individual test structures using a contactless medium;

measuring electrical or optical activity from at least some of the plurality of test structures on which the corresponding signal is generated;

correlating the measured electrical or optical activity for individual test structures to a corresponding performance parameter;

performing analysis using the performance parameter of each of the individual test structures in order to evaluate performance of one or more fabrication steps in the fabrication of the wafer.

2. The method of claim 1, wherein generating a corresponding signal includes using illumination to generate the signal from each of the plurality test structures.

3. The method of claim 2, wherein using illumination includes directing a laser onto a photodiode that is part of or connected to one or more of the plurality of test structures.

4. The method of claim 1, wherein generating a corresponding signal includes using an e-beam to generate the signal from each of the plurality test structures.

5. The method of claim 1, further comprising selecting a structure for one or more of the test structures to be indicative of a presence of an electrical or physical characteristic of the die and/or the wafer.

6. The method of claim 1, wherein selecting a structure for one or more of the test structures includes selecting a dimension or arrangement of one or more ring oscillators that are to comprise an individual one of the test structures.

7. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:

identifying a location on a die of the wafer for each of a plurality of test structures;

when the wafer is in a partially fabricated form, generating a corresponding signal from each of the plurality of test structures by directing energy onto the individual test structures using a contactless medium;

measuring electrical or optical activity from at least some of the plurality of test structures on which the corresponding signal is generated;

correlating the measured electrical or optical activity for individual test structures to a corresponding performance parameter;

performing analysis using the performance parameter of each of the individual test structures in order to evaluate a design of at least a portion of the wafer.

8. The method of claim 7, further comprising performing analysis using the performance parameter of each of the individual test structures in order to evaluate a layout of at least a portion of the die.

9. The method of claim 7, wherein generating a corresponding signal includes using illumination to generate the signal from each of the plurality test structures.

10. The method of claim 8, wherein using illumination includes directing a laser onto a photodiode that is part of or connected to one or more of the plurality of test structures.

11. The method of claim 7, wherein generating a corresponding signal includes using an e-beam to generate the signal from each of the plurality test structures.