Method for booting a host device from an MMC/SD device, a host device bootable from an MMC/SD device and an MMC/SD device method a host device may booted from

• US 7,739,487 B2
• Filed: 01/17/2006
• Issued: 06/15/2010
• Est. Priority Date: 01/17/2006
• Status: Active Grant

• Current Assignee: Memory Technologies LLC (Pendrell Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Ahvenainen, Marko, Mylly, Kimmo
• Primary Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US11/333,799
• Publication Number:
  US 20070168652A1
• Time in Patent Office: 1,610 Days
• Field of Search: 713/1, 713/2, 710/307, 710/315, 710/316, 711/115, 235/492
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

Systems and methods for booting a host device(s) from a peripheral device(s), via an interface, such as an MMC/SD interface, with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal. Power is provided to the power terminals, and the command terminal of the MMC/SD or analogous interface is set during power-up to low. The data bus is monitored for a start bit of data transmission.

Claims

1. A method for booting a host device from a peripheral device, via an MMC/SD interface with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal, said method comprising:

providing power to said power terminals,

setting the command terminal of said MMC/SD interface during power-up to low, and

monitoring the data bus for a start bit of a data transmission.

2. A method according to claim 1, said method further comprising sending a clock signal from said host device to said clock terminal of said MMC/SD interface, wherein said command terminal of said MMC/SD interface is set to low before or during power-up process during the transmission of between 24 to 148, preferably between 60 and 100 and most preferably to 74 initialization clock cycles.

3. A method according to claim 1, said method further comprising sending a clock signal from said host device to said clock terminal as long as the device has sent the data via said data bus.

4. A method according to claim 1, wherein said data bus terminals, said method further comprising setting the data bus terminals to low, to indicate a width for the data bus to be used for the data transfer.

5. A computer readable medium encoded with a computer program comprising program code sections for carrying out the method of claim 1, when said program is run on a host device, a peripheral device having an MMC/SD-interface or a system of host device with an inserted peripheral device having an MMC/SD-interface.

6. A method for booting from a peripheral device having an MMC/SD-interface, via said MMC/SD interface with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal, said method comprising:

receiving power at said power terminals of said MMC/SD-interface,

receiving a low signal at the command terminal before or during power up, and

sending the first data of a predefined storage area via data bus, starting with a start bit of the first data frame.

7. A method according to claim 6, wherein said first data of a predefined storage area via data bus, are only send if and when receiving a low signal at said command terminal of said MMC/SD-interface during power-up process during the transmission of between 24 to 148, preferably between 60 and 100 and most preferably to 74 initialization clock cycles.

8. A method according to claim 6, further comprising:

receiving a low signal at the data bus terminals, indicating a width for the data bus to be used for the transfer by, and

sending said data using the indicated data bus width.

9. A computer readable medium encoded with a computer program comprising program code sections for carrying out the method of claim 6, when said program is run on a host device, a peripheral device having an MMC/SD-interface or a system of host device with an inserted peripheral device having an MMC/SD-interface.

10. A method for booting a host device from a peripheral device having an MMC/SD-interface with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal, said method comprising:

sending during an initialization procedure an argument for a boot request from said host device via said MMC/SD-interface to the peripheral device,

sending a clock signal to the clock line, and

monitoring the data bus for a start bit of a data transmission.

11. A computer readable medium encoded with a computer program comprising program code sections for carrying out the method of claim 10, when said program is run on a host device, a peripheral device having an MMC/SD-interface or a system of host device with an inserted peripheral device having an MMC/SD-interface.

12. A method according to claim 10, further comprising:

sending additional arguments indicating parameters related to the boot sequence selected from the group of

number of data lines to be used for the boot sector read, and

clock frequency/timing mode to be used,

along with argument for the boot request from said host device to the MMC/SD-interface.

34. A method according to claim 10, wherein said argument for a boot request comprises a command.

35. A method according to claim 10, wherein said argument for a boot request is sent during or directly after the CMD0 phase.

36. A method according to claim 35, wherein said argument for a boot request comprises a reset command during the CMD0 phase.

37. A method according to claim 10, wherein said argument for a boot request comprises an argument for CMD0 command.

38. A method according to claim 10, wherein said argument for a boot request comprises an argument for an amended CMD0 command.

13. A method for booting a host device from a peripheral device having an MMC/SD-interface with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal, said method comprising:

receiving during an initialization procedure of the peripheral device an argument for a boot request from said host device at said MMC/SD-interface of the peripheral device,

receiving a clock signal at the clock terminal, and

sending data starting with a start bit of a data transmission to said host device via said MMC/SD-interface, if and when boot data are stored in said peripheral device.

14. A method according to claim 13, further comprising receiving additional arguments indicating parameters related to the boot sequence selected from the group of

number of data lines to be used for the boot sector read, and

clock frequency/timing mode to be used for a data transmission, along with said argument for the boot request from said host device, and using said indicated parameters for transmitting data via said data bus to said host device.

15. A computer readable medium encoded with a computer program comprising program code sections for carrying out the method of claim 13, when said program is run on a host device, a peripheral device having an MMC/SD-interface or a system of host device with an inserted peripheral device having an MMC/SD-interface.

39. A method according to claim 13, wherein said argument for a boot request comprises a command.

40. A method according to claim 13, wherein said argument for a boot request is sent during or directly after the CMD0 phase.

41. A method according to claim 40, wherein said argument for a boot request comprises a reset command during the CMD0 phase.

42. A method according to claim 13, wherein said argument for a boot request comprises an argument for CMD0 command.

43. A method according to claim 13, wherein said argument for a boot request comprises an argument for an amended CMD0 command.

16. A bootable host device configured for being booted from a peripheral device having an MMC/SD-interface, said host device comprising:

a power supply,

a processor connected to said power supply, and

an MMC/SD-interface connected to said processor and to said power supply, said MMC/SD interface with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal,

wherein said host device is configured for providing power to the terminals of said MMC/SD-interface, and setting the command terminal of said MMC/SD-interface during power-up to low, and monitoring the data bus for a start bit of a data transmission.

17. A bootable host device according to claim 16, wherein said processor is configured to send a clock signal from said host device to said data bus terminals of said MMC/SD-interface and to set the command terminal of said MMC/SD-interface during power-up process to low while transmitting between 24 and 148, preferably between 60 and 100 and most preferably 74 initialization clock cycles.

18. A bootable host device according to claim 16, wherein said processor is further configured to send a clock signal from said host device to said data bus terminals of said MMC/SD-interface as long as the MMC/SD device starts to send the first data via said data bus.

19. A bootable host device according to claim 16, wherein said processor is configured to set the data bus terminals to low, to indicate a width for the data bus to be used for the transfer by a peripheral device having an MMC/SD-interface inserted in said MMC/SD-interface.

20. A peripheral device having an MMC/SD-interface configured for booting a bootable host device configured for being booted from a peripheral device having an MMC/SD-interface, said peripheral device comprising:

an MMC/SD-interface, provided with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal,

a peripheral device controller, connected to said MMC/SD-interface,

a memory module, connected to said peripheral device controller, and

wherein said peripheral device controller is configured for sending the first data of a predefined storage area via a data bus, starting with a start bit of the first data frame, when receiving power at the terminals of said MMC/SD-interface of said peripheral device, and a low signal at the command terminal of said MMC/SD-interface during power-up.

21. A peripheral device according to claim 20, wherein said peripheral device controller is further configured to send said first data of a predefined storage area via data bus, only when receiving a low signal at said command terminal of said MMC/SD-interface before or during power-up process during the transmission of between 24 to 148, preferably between 60 and 100 and most preferably to 74 initialization clock cycles.

22. A peripheral device according to claim 20, wherein said peripheral device controller is further configured to:

receive a low signal at the data bus terminals of said MMC/SD-interface, indicating a width for the data bus to be used for the transfer by, and

sending said data using the indicated data bus width.

23. A bootable host device configured for being booted from a peripheral device having an MMC/SD interface, said host device comprising:

a power supply,

a processor connected to said power supply, and

an MMC/SD-interface connected to said processor and to said power supply, said MMC/SD-interface having power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal; and

wherein said host device is configured for;

sending during an initialization process of the peripheral device an argument for a boot request from said host device via said MMC/SD-interface to the peripheral device, and

monitoring the data bus for a start bit of a data transmission.

24. A bootable host device according to claim 23, wherein said host device is configured for sending additional arguments via said MMC/SD-interface, said additional arguments indicating parameters related to the boot sequence selected from the group of

number of data lines to be used for the boot sector read, and

clock frequency/timing mode to be used,

along with said argument for the boot request from said host device to said MMC/SD-interface.

25. A bootable host device according to claim 23, wherein said host device is further configured, to set the data bus terminals of said MMC/SD-interface to low, for indicating a width for the data bus to be used for the transfer.

44. A bootable host device according to claim 23, wherein said host device is configured for using an argument for a boot request that comprises a command.

45. A bootable host device according to claim 23, wherein said host device is configured for using an argument for a boot request that is sent during or directly after the CMD0 phase.

46. A bootable host device according to claim 45, wherein said host device is configured for using an argument for a boot request that comprises a reset command sent during the CMD0 phase.

47. A bootable host device according to claim 23, wherein said host device is configured for using an argument for a boot request comprising an argument for CMD0 command.

48. A bootable host device according to claim 23, wherein said host device is configured for using an argument for a boot request comprising an argument for an amended CMD0 command.

26. A peripheral device configured for booting a bootable host device configured for being booted from an peripheral device, said peripheral device comprising

an MMC/SD-interface, comprising power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal,

a peripheral device controller, connected to said MMC/SD-interface,

a memory module, connected to said peripheral device controller, and

wherein said peripheral device being configured for sending data starting with a start bit of a data transmission via said MMC/SD-interface to said host device, in case boot data are stored in the peripheral device, if and when receiving an argument for a boot request from said host device at said MMC/SD-interface of the peripheral device, and when receiving a clock signal at the clock line.

27. A peripheral device according to claim 26, wherein said peripheral device controller is further configured to receive a low signal at the data bus terminals of said MMC/SD-interface terminal indicating a width for the data bus to be used for the transfer and wherein said peripheral device controller is further configured for using said indicated data bus width for the data bus to be used for the transfer.

28. A peripheral device according to claim 26, wherein said peripheral device controller is further configured to receive along with argument for the boot request from said host device, additional arguments indicating parameters related to the boot sequence selected from the group of

number of data lines to be used for the boot sector read, and

clock frequency/timing mode to be used, and is further configured to send said data via said data bus to said host device according to said indicated parameters.

49. A peripheral device according to claim 26, wherein said peripheral device controller is further configured to receive an argument for a boot request comprising a command.

50. A peripheral device according to claim 26, wherein said peripheral device controller is further configured to receive an argument for a boot request during or directly after the CMD0 phase.

51. A peripheral device according to claim 50, wherein said peripheral device controller is further configured to receive an argument for a boot request comprising a reset command during the CMD0 phase.

52. A peripheral device according to claim 26, wherein said peripheral device controller is further configured to receive an argument for a boot request comprising an argument for CMD0 command.

53. A peripheral device according to claim 26, wherein said peripheral device controller is further configured to receive an argument for a boot request comprising an argument for an amended CMD0 command.

29. A bootable host device configured for being booted from a peripheral device having an MMC/SD interface, said host device comprising

a power supply,

a processor connected to said power supply, and

an MMC/SD-interface connected to said processor and to said power supply, said MMC/SD-interface having power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal,

wherein said host device is configured for

starting a standard initialization data exchange of a peripheral device having an MMC/SD interface via said MMC/SD-interface until a stand-by-state of said peripheral device is reached, and

performing a data exchange between said host device and said peripheral device from said stand-by-state for searching for a valid boot code in the components in bus.

30. A bootable host device configured for being booted from a peripheral device having an MMC/SD interface, wherein said peripheral device is provided with an Operation Condition Register with an additional argument for a boot request, said host device comprising

a power supply,

a processor connected to said power supply, and

an MMC/SD-interface connected to said processor and to said power supply, said MMC/SD-interface having power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal,

wherein said host device is configured for

sending after initialization of a peripheral device having an MMC/SD interface an argument for a boot request to said MMC/SD-interface, and

monitoring the data bus for boot data to be received from said peripheral device via said MMC/SD-interface.

31. A peripheral device having a MMC/SD interface configured for booting a bootable host device configured for being booted from a peripheral device having an MMC/SD interface, wherein said peripheral device is provided in the Operation Condition Register with an additional argument for a boot request said peripheral device comprising

an MMC/SD-interface, comprising power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal,

a peripheral device controller with a Operation Condition Register, connected to said MMC/SD-interface, and

a memory module, connected to said peripheral device controller,

wherein said peripheral device is provided in the Operation Condition Register with an additional argument for a boot request, and said peripheral device being configured for

receiving after an initialization procedure an argument for a boot request at the peripheral device, and

retrieving and sending boot data from the peripheral device memory module via said MMC/SD-interface to said host device.

32. A peripheral device having an MMC/SD interface according to claim 31, wherein said Operation Condition Register with said argument for a boot request is implemented as a hard coded hardware component, connected to or implemented in said peripheral device controller.

33. A peripheral device having an MMC/SD interface according to claim 31, wherein said Operation Condition Register with said argument for a boot request is implemented as software running in peripheral device controller.