Low power consumption MIS semiconductor device

• US 7,741,869 B2
• Filed: 01/24/2008
• Issued: 06/22/2010
• Est. Priority Date: 10/25/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hidaka, Hideto
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US12/010,427
• Publication Number:
  US 20080122479A1
• Time in Patent Office: 880 Days
• Field of Search: 326/34, 326/93, 326/95, 326/98, 326/121, 326/83, 326/33, 326/17, 327/544, 327/546
• US Class Current: 326/34
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Claims

1. A semiconductor device comprising:

a logic gate including, as a component, an insulated gate field effect transistor having a first gate insulating film, receiving a voltage on a first internal power node as an operating power supply voltage and processing a received signal;

a first switching transistor having a gate insulation film greater in thickness than said first gate insulation film, and electrically coupling a first power source node with said first internal power node responsive to a switch control signal; and

a precharge circuit selectively enabled in response to an operation mode instructing signal instructing a mode of operation of said logic gate and precharging said first internal power node to a prescribed voltage level different from the voltage level of said first power source node when enabled.

2. The semiconductor device according to claim 1, wherein said switch control signal is generated in accordance with a mode of operation of said logic gate and is greater in amplitude than said received signal of said logic gate.

3. The semiconductor device according to claim 1, wherein said logic gate receiving a voltage of said first internal power node and a voltage of a second internal power node as operating power supply voltages, and

said semiconductor device further comprises

a second switching transistor connected between said second internal power node and a second power source node, being different in conductivity type from said first switching transistor, having a gate insulation film greater in thickness than said first gate insulation film, and turning conductive in a common phase with said first switching transistor responsive to said switch control signal, and

said precharge circuit precharges the first and second internal power nodes to a level intermediate between the voltage of said first power source node and the voltage of said second power source node.

4. A semiconductor device comprising:

a logic gate including, as a component, an insulated gate field effect transistor having a first gate insulating film, receiving a voltage on a first internal power node as an operating power supply voltage and processing a received signal;

a first switching transistor having a gate insulation film greater in thickness than said first gate insulation film, and electrically coupling a first power source node with said first internal power node responsive to a switch control signal; and

a precharge circuit selectively enabled in response to an operation mode instructing signal instructing a mode of operation of said logic gate and precharging said first internal power node to a prescribed voltage level different from said operating power supply voltage level when enabled.