Multi-thread graphics processing system

• US 7,742,053 B2
• Filed: 05/09/2007
• Issued: 06/22/2010
• Est. Priority Date: 09/29/2003
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Gruber, Andrew E., Morein, Stephen L., Lefebvre, Laurent
• Primary Examiner(s): Nguyen; Hau H
• Application Number:
  US11/746,453
• Publication Number:
  US 20070222787A1
• Time in Patent Office: 1,140 Days
• Field of Search: 345/522, 345502-505, 345/556, 345/558, 345/535
• US Class Current: 345/522
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Claims

1. A graphics processing system comprising:

at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads; and

an arbiter, coupled to the at least one memory device, operable to select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads.

2. The graphics processing system of claim 1, further comprising:

a command processing engine, coupled to the arbiter, wherein the arbiter is further operable to provide the command thread to the command processing engine.

3. The graphics processing system of claim 1, wherein the first portion of the at least one memory device comprises a first memory device and the second portion of the at least one memory device comprises a second memory device.

4. The graphics processing system of claim 1, wherein a single memory device comprises the first portion and the second portion of the at least one memory device.

5. A graphics processing system comprising:

at least one memory device comprising a first portion operative to store a plurality of pixel command threads and a second portion operative to store a plurality of vertex command threads;

an arbiter, coupled to the at least one memory device, operable to select a command thread from either of the plurality of pixel command threads and the plurality of vertex command threads; and

a plurality of command processing engines, coupled to the arbiter, each operable to receive and process the command thread.

6. The graphics processing system of claim 5, wherein the plurality of command processing engines comprises at least one arithmetic logic unit.

7. The graphics processing system of claim 5, wherein the plurality of command processing engines comprises at least one texture processing engine.

8. The graphics processing system of claim 5, wherein the first portion of the at least one memory device comprises a first memory device and the second portion of the at least one memory device comprises a second memory device.

9. The graphics processing system of claim 5, wherein a single memory device comprises the first portion and the second portion of the at least one memory device.