Method and system for providing spin transfer tunneling magnetic memories utilizing non-planar transistors

• US 7,742,328 B2
• Filed: 06/15/2007
• Issued: 06/22/2010
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Driskill-Smith, Alexander A. G., Huai, Yiming, Chen, Eugene
• Primary Examiner(s): Elms; Richard
• Assistant Examiner(s): Byrne; Harry W
• Application Number:
  US11/764,057
• Publication Number:
  US 20080310213A1
• Time in Patent Office: 1,103 Days
• Field of Search: 365/66, 365 80- 85, 365/100, 365/148, 365/158, 365/171, 365/173, 365/225.5, 365/243.5, 257/421, 257/E21.665, 438/3, 977933-935
• US Class Current: 365/158
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: Y10S 977/935 Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR

Abstract

A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

Claims

1. A magnetic memory cell comprising:

at least one magnetic element, the at least one magnetic element being programmable using at least one write current driven through the magnetic element; and

at least one non-planar selection device coupled with the at least one magnetic element.

2. The magnetic memory cell of claim 1 wherein the at least one non-planar selection device further includes a non-planar transistor.

3. The magnetic memory cell of claim 2 wherein the non-planar transistor includes at least one of a multiple gate transistor;

a silicon on oxide (SOI) transistor, a type of Fin field effect transistor (FinFET), a multiple-gate SOI transistor, a nanowire transistor, a (carbon) nanotube transistor, a delta transistor, a folded channel transistor, a triangular wire transistor, a vertical channel transistor, a vertical-source planar gate transistor, and a round-gate transistor.

4. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one non-planar selection device, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

a plurality of bit lines corresponding to the plurality of magnetic storage cells; and

a plurality of source lines corresponding to the plurality of magnetic storage cells.

5. The magnetic memory of claim 4 wherein the at least one non-planar selection device further includes a non-planar transistor.

6. The magnetic memory of claim 5 wherein the non-planar transistor includes at least one of a multiple gate transistor;

a silicon on oxide (SOI) transistor, a type of Fin field effect transistor (FinFET), a multiple-gate SOI transistor, a nanowire transistor, a (carbon) nanotube transistor, a delta transistor, a folded channel transistor, a triangular wire transistor, a vertical channel transistor, a vertical-source planar gate transistor, and a round-gate transistor.

7. The magnetic memory of claim 5 wherein the at least one magnetic element includes at least one pinned layer, at least one spacer layer, and at least one free layer, the at least one spacer layer residing between the at least one pinned layer and the at least one free layer.

8. The magnetic memory of claim 7 wherein the at least one spacer layer includes at least one insulator configured to allow tunneling of charge carriers through the at least one insulator.

9. The magnetic memory of claim 8 wherein the at least one magnetic element includes a magnetic tunneling junction.

10. The magnetic memory of claim 8 wherein the at least one magnetic element includes at least one dual magnetic tunneling junction.

11. The magnetic memory of claim 4 further comprising:

a plurality of write assist lines corresponding to the plurality of magnetic storage cells, the plurality of write assist lines for providing a magnetic field during a write of at least a portion of the plurality of magnetic memory cells.

12. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one non-planar transistor, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

a plurality of bit lines corresponding to the plurality of magnetic storage cells;

providing and

a plurality of source lines corresponding to the plurality of magnetic storage cells;

wherein the non-planar transistor includes at least one of a multiple gate transistor;

a silicon on oxide (SOI) transistor, a type of Fin field effect transistor (FinFET), a multiple-gate SOI transistor, a nanowire transistor, a (carbon) nanotube transistor, a delta transistor, a folded channel transistor, a triangular wire transistor, a vertical channel transistor, a vertical-source planar gate transistor, and a round-gate transistor.

13. The magnetic memory of claim 12 further comprising:

a plurality of write assist lines corresponding to the plurality of magnetic storage cells, the plurality of write assist lines for providing a magnetic field during a write of at least a portion of the plurality of magnetic memory cells.

14. A method for fabricating a magnetic memory comprising:

providing a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic element and at least one non-planar selection device, the at least one magnetic element being programmable using at least one write current driven through the magnetic element;

providing a plurality of bit lines corresponding to the plurality of magnetic storage cells;

providing and

providing a plurality of source lines corresponding to the plurality of magnetic storage cells.

15. The method of claim 14 wherein the at least one non-planar selection device further includes a non-planar transistor.

16. The method of claim 15 wherein the non-planar transistor includes at least one of a multiple gate transistor;

a silicon on oxide (SOI) transistor, a type of Fin field effect transistor (FinFET), a multiple-gate SOI transistor, a nanowire transistor, a (carbon) nanotube transistor, a delta transistor, a folded channel transistor, a triangular wire transistor, a vertical channel transistor, a vertical-source planar gate transistor, and a round-gate transistor.

17. The method of claim 14 wherein the at least one magnetic element includes at least one pinned layer, at least one spacer layer, and at least one free layer, the at least one spacer layer residing between the at least one pinned layer and the at least one free layer.

18. The method of claim 17 wherein the at least one spacer layer includes at least one insulator configured to allow tunneling of charge carriers through the at least one insulator.

19. The method of claim 17 wherein the at least one magnetic element includes at least one of a magnetic tunneling junction and a dual magnetic tunneling junction.

20. The method of claim 14 further comprising:

providing a plurality of write assist lines corresponding to the plurality of magnetic storage cells, the plurality of write assist lines for providing a magnetic field during a write of at least a portion of the plurality of magnetic memory cells.