On-chip shared memory based device architecture

• US 7,743,191 B1
• Filed: 12/20/2007
• Issued: 06/22/2010
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Liao, Heng
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US11/961,402
• Time in Patent Office: 915 Days
• Field of Search: 710110-113, 710/116, 710/121, 710/123, 710308-310, 710/316, 710/317, 710240-242, 710/244, 710/246, 711/148, 711/150, 711/151, 711/168, 711/209
• US Class Current: 710/240
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G11B 2020/10759 content data
• CPC Class Codes: G11B 2020/10787 parameters, e.g. for decoding or encoding
• CPC Class Codes: G11B 2220/415 Redundant array of inexpensive disks [RAID] systems

Abstract

A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.

Claims

1. A system-on-a-chip device comprising:

a plurality of parallel masters;

a global shared memory switch (GSM) structurally related as a slave with respect to the plurality of parallel masters and in communication therewith, the GSM including on-chip shared memory resources to provide an interconnect mechanism among hardware components, processors and software entities, the GSM arranged to arbitrate among the plurality of parallel masters to allow the plurality of parallel masters to concurrently access the shared memory resources;

the plurality of parallel masters including a processor complex subsystem and a memory interface controller,

the processor complex subsystem including a high priority processor and one or more low priority processors;

the memory interface controller, to manage memory access requests for a plurality of memory interfaces external to the processor complex subsystem;

the system-on-a-chip device further including,

a dedicated low latency physical path from the high priority processor to the memory interface controller to prioritize traffic from the high priority processor; and

an arbitrated physical path from the low priority processors to the memory interface controller, the arbitrated physical path having a higher latency than the dedicated low latency physical path,

wherein the GSM comprises,

a system wide GSM with high port count to connect all subsystems together; and

a smaller GSM with ports only connecting to the CPUs and the storage interface controller subsystem to provide context and/or queue storage for the storage controller.

2. The device of claim 1 wherein the GSM is provided as a primary interconnect and buffering mechanism for both a control path and a data path.

3. The device of claim 1 wherein the GSM comprises a unified addressing scheme for all on-chip resources, such that each processor has equal access to the resources via the unified addressing scheme.

4. The device of claim 1 wherein the plurality of memory interfaces comprise a double data rate (DDR) memory interface and a peripheral component interconnect (PCI) memory interface, and each processor has access to both DDR and PCI memory using the same addressing scheme.

5. The device of claim 1 wherein the GSM comprises on-chip GSM structures to store context, queue and buffer structures that are shared between processors and hardware controllers.

6. The device of claim 1 wherein the GSM comprises buffer space based on large RAMs to provide shared RAM space across receive and transmit paths of multiple high bandwidth channels that are implemented as separate hardware blocks, permitting the buffer space to be flexibly reassigned or dynamically shared based on configuration or buffer sharing policy.

7. The device of claim 1 wherein the GSM comprises GSM queues to communicate operation requests and/or operation results between a requestor and processing engines.

8. The device of claim 1 wherein the GSM comprises GSM buffers to store the source and destination data blocks.

9. The device of claim 1 wherein the GSM comprises context storage to store context information required to support concurrent operations.

10. The device of claim 1 wherein the GSM utilizes parallel random access memory (RAM) instances to strip data in order to provide high aggregate on-chip shared memory bandwidth for concurrent access across multiple masters.

11. The device of claim 1 wherein the on-chip shared memory resources comprise a global ring buffer including configurable sets of first in first out registers (FIFOs).

12. The device of claim 11 wherein the global ring buffer provides hardware signals to indicates a status of the FIFOs within the ring buffer that can be routed and multiplexed to various GSM masters, so that the hardware operations/CPU interrupts/events can be triggered by ring buffer status change.

13. The device of claim 1 wherein the dedicated low latency physical path has low arbitration latency characteristics and low physical path latency to memory.

14. The device of claim 1 further comprising, for each CPU:

a low speed arbitrated configuration bus for device configuration and maintenance, to provide accessibility from any CPU or external master to internal hardware configuration and status information without interference of high speed, high bandwidth control and data traffic.

15. The device of claim 1 further comprising:

an interrupt/event handler to categorize interrupt/event sources as latency critical and latency non-critical sources; and

a direct crossbar to handle the latency critical sources and allow full programmability of connecting any critical interrupt source to any processor input pin.

16. The device of claim 15 further comprising:

an interrupt/event bus; and

a plurality of interrupt/event gaskets, one for each processor, connected to the interrupt/event bus, each interrupt/event gasket providing programmable demultiplexing functions that allow each processor interrupt signal to take a value of a programmable time slot and bit position within the interrupt/event bus.