Managing flash memory based upon usage history

• US 7,743,203 B2
• Filed: 05/11/2007
• Issued: 06/22/2010
• Est. Priority Date: 05/11/2007
• Status: Active Grant

• Current Assignee: Valley Device Management
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: France, Robert Brent
• Primary Examiner(s): Peugh; Brian R
• Assistant Examiner(s): SIMONETTI, NICHOLAS J
• Application Number:
  US11/747,608
• Publication Number:
  US 20080279005A1
• Time in Patent Office: 1,138 Days
• Field of Search: 711/103, 365/185.29, 365/185.3, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A memory management component can track the amount of time between erase cycles for a particular memory region, and can manage memory region such that the regions are given sufficient time to rest and recover, or are given at least as much rest time as is practical, before being subject to an erase cycle. A reclamation management component can reclaim memory region that have invalid data stored therein, and can reclaim regions on a just-in-time basis when practical, and can determine which regions to reclaim based on various factors, such as the amount of time since a region was last erased, and the number of programming errors associated with a region. The memory management component can thereby optimize the useful life, minimize or reduce loss of margin in memory regions, and minimize or reduce programming errors of memory regions, of non-volatile (e.g., flash) memory.

Claims

1. A system that facilitates management and lifetime optimization of a memory, comprising:

the memory comprising a plurality of memory regions;

a processor;

a computer readable storage medium operationally coupled to the processor and storing computer executable instructions, the computer executable instructions, when executed by the processor, implement components comprising;

a cycle interval management component that compiles a history of usage and operating conditions of a memory region of the plurality of memory regions and, based at least on the history of usage and operating conditions, identifies an additional period of time for which the memory region should be rested following an erase cycle, wherein the additional period of time the memory should be rested is in addition to a period of time the memory region rests after an erase cycle on the memory region is performed, and

a memory management component that determines if an operation is to be performed on the memory region based in part on the additional period of time for which the memory region should be rested.

2. The system of claim 1, the operation is one of a write operation, a reclaiming operation, or an erase cycle.

3. The system of claim 2, further comprising a data management component that facilitates placing data associated with the write operation in one or more memory regions by employing at least one of address translation, peanut-butter wear leveling where data is striped through memory regions, in-order wear leveling, pseudo-wear leveling, dynamic wear leveling, or static wear leveling, or a combination thereof.

4. The system of claim 2, the reclaiming operation is one of a just-in-time memory region reclamation, a background memory region reclamation, or an on-demand memory region reclamation.

5. The system of claim 4, the just-in-time memory region reclamation is performed if an amount of empty space in the memory is below a predetermined threshold level.

6. The system of claim 1, the memory management component determines if the operation is to be performed on the memory region based in part on a number of programming errors associated with the memory region.

7. The system of claim 1, further comprising a memory region reclamation component that identifies a memory region of the plurality of memory regions to be reclaimed, distinguishes between valid and invalid data in the memory region, facilitates the transfer of valid data from the memory region to another memory region of the plurality of memory regions, and facilitates an erase of the memory region to reclaim the memory region.

8. The system of claim 1, the cycle interval management component tracks an amount of time the memory, or a device in which the memory resides, is powered on;

records the amount of time; and

generates a normalized amount of time, where the amount of time is normalized to account for periods of time where the memory or the device is not powered on.

9. The system of claim 1, the cycle interval management component facilitates placement of information associated with an erase of a memory region in at least a list, a table, or a tree, or a combination thereof.

10. The system of claim 1, the memory is non-volatile memory, comprising flash memory.

11. A device comprising the system of claim 1, the device further comprising at least one of a computer, a personal digital assistant, a cellular phone, a digital phone, an answering machine, a video device, a television, a digital versatile diskplayer/recorder, a music player/recorder, an MP3 player, a digital recorder, a digital camera, a microwave oven, an electronic organizer, an electronic toy, an electronic game, a scanner, a reader, a printer, a copy machine, or a facsimile machine.

12. The system of claim 1, further comprising a burst pool component that facilitates maintaining a burst pool that comprises a number of memory regions associated with the memory that are placed in the burst pool and are made available when there are no memory regions left in an available pool of memory regions associated with the memory.

13. A method for managing and optimizing a memory, comprising:

employing a processor executing computer executable instructions stored on a computer readable storage medium to implement the following acts;

compiling a history of usage and operating conditions for at least one memory region of a plurality of memory regions in the memory;

determining a period of time for which the at least one memory region should be rested following an erase cycle in which the period of time is in addition to a rest period for the memory region in a dormant state, the dormant state is when the memory region is in the process of erasing or when the erase of the memory region has just been completed;

initiating an operation associated with the memory, the operation is one of a write operation, a memory region reclaiming operation, or an erase cycle; and

determining the at least one memory region of the plurality of memory regions in the memory on which the operation is to be performed based in part on the determined rest time period in addition to a rest period of the at least one memory region in a dormant state.

14. The method of claim 13, further comprising:

selecting the at least one memory region; and

performing the operation on the at least one memory region.

15. The method of claim 13, further comprising:

determining the at least one memory region on which the operation is to be performed based in part on one of a number of programming errors or an average number of programming errors per erase cycle, associated with the memory region.

16. The method of claim 13, further comprising:

selecting a recovered memory region with a number of programming errors that is below a predetermined threshold value, if there is such recovered memory region in at least one of an available pool or a burst pool, where the operation is a write operation;

selecting a well-rested erased memory region with a number of programming errors that is below a predetermined threshold value, if there is such well-rested erased memory region in at least one of an available pool or a burst pool, where the operation is a write operation;

selecting an erased memory region with a number of programming errors that is below a predetermined threshold value, if there is no recovered memory region or well-rested erased memory region with a number of programming errors that is below a predetermined threshold value in the at least one of the available pool or the burst pool, and if there is an erased memory region in the at least one of the available pool or the burst pool; and

selecting an empty memory region with a number of programming errors that is at or above a predetermined threshold value, if there is no recovered memory region, well-rested erased memory region, or erased memory region with a number of programming errors that is below a predetermined threshold value in the at least one of the available pool or the burst pool.

17. The method of claim 16, further comprising:

reclaiming one or more memory regions, if there are no empty memory regions in the at least one of the available pool or the burst pool.

18. The method of claim 13, further comprising:

initiating a just-in-time memory region reclamation if the number of available memory regions is below a predetermined threshold level;

reclaiming a memory region of the plurality of the memory regions if the memory region is well rested, if one or more such well-rested memory region are available;

reclaiming a memory region of the plurality of the memory region if the memory region has a low number of programming errors, if one or more such low-error memory region are available and if no well-rested memory region is available; and

reclaiming a memory region of the plurality of the memory region if the memory region has a low amount of valid data stored therein, if one or more such memory region with low amount of valid data are available, and if a well-rested memory region and a low-error memory region are not available.

19. A system for managing memory regions in a memory, comprising:

a processor;

a computer readable storage medium storing computer executable instructions, the computer executable instructions, when executed by the processor, implement components comprising;

means for selecting, by the processor, a type of data placement to be utilized during a write operation;

means for compiling, by the processor, a usage and operating condition history of at least one memory region in a plurality of memory regions in the memory;

means for identifying, by the processor, a default period of time for which at least one memory region is rested following an erase cycle, such default period of time relates to a usage and operating condition history;

means for determining, by the processor, an additional period of time for which the at least one memory region should be rested following an erase cycle based upon the usage and operating condition history, such additional period of time is in addition to the default period of time for which at least one memory region is rested following an erase cycle;

means for calculating, by the processor, an amount of time since an erase cycle has been performed on the at least one memory region;

means for determining, by the processor, whether the at least one memory region has rested for the determined rest period since the erase cycle was performed on the at least one memory region; and

means for choosing, by the processor, at least one memory region of the plurality of memory regions on which to execute the write operation based in part on whether the at least one memory region has been sufficiently rested.

20. The system of claim 19, further comprising:

means for reclaiming at least one memory region of the plurality of memory regions based in part on at least one of a period of time since an erase cycle has been performed on the at least one memory region or a number of programming errors associated with the at least one memory region, or a combination thereof;

means for determining if an occupancy level associated with the memory exceeds a predetermined threshold level; and

means for determining a type of memory region reclamation to perform based in part on whether the occupancy level exceeds the predetermined threshold level.