Nonvolatile semiconductor memory

• US 7,746,697 B2
• Filed: 03/11/2008
• Issued: 06/29/2010
• Est. Priority Date: 07/06/1992
• Status: Expired due to Fees

• Current Assignee: Emergence Memory Solutions LLC
• Original Assignee: Solid State Storage Solutions, Inc.
• Inventors: Tanaka, Toshihiro, Kato, Masataka, Kimura, Katsutaka, Adachi, Tetsuo, Kume, Hitoshi, Sasaki, Toshio
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/046,150
• Publication Number:
  US 20080219082A1
• Time in Patent Office: 840 Days
• Field of Search: 365/185.11, 365/185.28, 365/185.29
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Claims

1. A data storing apparatus comprising:

a controller; and

a plurality of nonvolatile memories,

wherein each of the nonvolatile memories comprises an address buffer for holding address information supplied from the controller and a plurality of sectors each comprising one word line and each of a plurality of nonvolatile memory cells connected thereto, and is capable of receiving data from the controller, in response to pulses supplied from the controller, and after then starts to program data in sector units as selected by the address information, and

wherein the controller (i) transfers data to a first nonvolatile memory of the plurality of nonvolatile memories in response to supplying the pulses to the first nonvolatile memory, (ii) stops supplying the pulses to the first nonvolatile memory with ending of the data outputting, and after then (iii) is capable of starting the transfer of data to a second nonvolatile memory of the plurality of nonvolatile memories in response to supplying the pulses to the second nonvolatile memory.

2. A data storing apparatus according to claim 1,

wherein the controller supplies address information to a corresponding nonvolatile memory before supplying data.

3. A data storing apparatus according to claim 2,

wherein the controller is supplied with first address information from outside of the data storing apparatus, and comprises a decoder means for selecting one of the nonvolatile memories in accordance with the first address information.

4. A data storing apparatus according to claim 3,

wherein each of the nonvolatile memories further comprises an address decoder coupled to the word lines thereof, and each of the nonvolatile memories selects a sector in accordance with the address information supplied from the controller and decoded by the address decoder thereof.

5. A data storing apparatus according to claim 4,

wherein each of the nonvolatile memories further comprises a data buffer for holding data supplied from the controller in units of a sector, temporarily.

6. A data storing apparatus according to claim 5,

wherein each sector contains a byte-size unit of 512 nonvolatile memory cells or an integer multiple thereof.

7. A data storing apparatus comprising:

a control circuit; and

a plurality of nonvolatile memories each of which comprises an address buffer and a nonvolatile memory array configured as a plurality of sectors, each sector comprising one word line and each of a plurality of nonvolatile memory cells connected thereto,

wherein each of the nonvolatile memories receives from the control circuit address information for holding in the address buffer thereof and data for programming into each nonvolatile memory array in units of a sector, and

wherein the control circuit supplies first address information and first data to a first nonvolatile memory of the plurality of nonvolatile memories, after then is capable of supplying second address information and second data to a second nonvolatile memory of the plurality of nonvolatile memories during programming of the first data in the first nonvolatile memory.

8. A data storing apparatus according to claim 7,

wherein an address from outside of the data storing apparatus is received, and

wherein the control circuit uses the address received from outside for selecting one of the nonvolatile memories to be supplied with the address information and data, and generates the address information to supply to the selected one of the nonvolatile memories.

9. A data storing apparatus according to claim 8, being coupled to a host system via a predetermined bus standard.

10. A data storing apparatus according to claim 9,

wherein the predetermined bus standard is the Intelligent Device Electronics (IDE) standard.

11. A data storing apparatus comprising:

a controller; and

at least a first nonvolatile memory and a second nonvolatile memory, each of which comprises an address buffer for holding address information supplied from the controller and plurality of sectors each comprising one word line and each of a plurality of nonvolatile memory cells connected thereto,

wherein each of the nonvolatile memories is coupled to receive data from the controller, in response to pulses supplied from the controller, and after then starts to program data into a respective sector selected by the address information, and

wherein the controller (i) transfers data to the first nonvolatile memory in response to supplying the pulses to the first nonvolatile memory, (ii) stops supplying the pulses to the first nonvolatile memory with ending of data outputting, and after then (iii) is enabled for starting the transfer of data to the second nonvolatile memory in response to supplying the pulses to the second nonvolatile memory.

12. A data storing apparatus according to claim 11,

wherein the controller supplies address information to a corresponding nonvolatile memory before supplying data.

13. A data storing apparatus according to claim 12,

wherein the controller is supplied with first address information from outside of the data storing apparatus, and comprises a decoder means for selecting one of the nonvolatile memories in accordance with the first address information.

14. A data storing apparatus according to claim 13,

wherein each of the nonvolatile memories further comprises an address decoder coupled to the word lines thereof, and each of the nonvolatile memories selects a sector in accordance with the address information supplied from the controller and decoded by the address decoder thereof.

15. A data storing apparatus according to claim 14,

wherein each of the nonvolatile memories further comprises a data buffer for holding data supplied from the controller in units of a sector, temporarily.

16. A data storing apparatus according to claim 15,

wherein each sector contains a byte-size unit of 512 nonvolatile memory cells or an integer multiple thereof.

17. A nonvolatile memory system comprising:

a plurality of nonvolatile memory devices;

a buffer memory; and

a circuit;

wherein said buffer memory is coupled to said circuit and is enabled to receive data from outside of said nonvolatile memory system via said circuit,

wherein each of said nonvolatile memory devices is coupled to said buffer memory, is enabled to store said data received therefrom in a programming operation and comprises a plurality of sectors each comprising one word line and each of a plurality of nonvolatile memory cells connected thereto,

wherein said buffer memory is enabled to receive data in units of a sector from outside of said nonvolatile memory system, while on of said nonvolatile memory devices is in said programming operation, and

wherein said buffer memory has a data storing capacity enabling the receiving of a unit of data of a length equal to a sector to be stored at one time of said programming operation.

18. A nonvolatile memory system according to claim 17,

wherein another one of said nonvolatile memory devices is enabled to receive said data received by said buffer memory and to start storing the received data, while said one of said nonvolatile memory devices is in said programming operation.

19. A nonvolatile memory system according to claim 18,

wherein said sector contains a byte-size unit of 512 nonvolatile memory cells or an integer multiple thereof.

20. A nonvolatile memory system according to claim 19,

wherein each of said nonvolatile memory devices is a flash memory chip.

21. A nonvolatile memory system according to claim 17,

wherein each of said nonvolatile memory devices is a flash memory chip.