Memory having a dummy bitline for timing control

  • US 7,746,716 B2
  • Filed: 02/22/2007
  • Issued: 06/29/2010
  • Est. Priority Date: 02/22/2007
  • Status: Active Grant
First Claim
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1. A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory comprising:

  • a plurality of sense amplifiers coupled to the at least one memory array block;

    at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells;

    at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N; and

    a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pulldown transistors coupled to a sense circuit for generating a sense trigger signal used to enable the plurality of sense amplifiers, wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using a dummy wordline.

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