Memory having a dummy bitline for timing control
DCFirst Claim
1. A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory comprising:
- a plurality of sense amplifiers coupled to the at least one memory array block;
at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells;
at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N; and
a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pulldown transistors coupled to a sense circuit for generating a sense trigger signal used to enable the plurality of sense amplifiers, wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using a dummy wordline.
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Abstract
A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.
39 Citations
20 Claims
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1. A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory comprising:
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a plurality of sense amplifiers coupled to the at least one memory array block; at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells; at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N; and a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pulldown transistors coupled to a sense circuit for generating a sense trigger signal used to enable the plurality of sense amplifiers, wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using a dummy wordline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory comprising:
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a plurality of sense amplifiers coupled to the at least one memory array block; at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells; at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N; and a timing circuit coupled to the at least one dummy bitline forming a node, wherein the timing circuit comprises at least one stack of pulldown transistors coupled to a sense circuit for generating a local reset signal used to precharge the node, wherein the local reset signal is generated based on at least a load characteristic of the at least one dummy bitline, wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using a dummy wordline. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for operating a memory comprising at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, the memory further comprising a plurality of sense amplifiers coupled to the at least one memory array block, at least one bit line comprising bitcells, wherein the N wordlines are used to select the bitcells, at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N, and a timing circuit, the method comprising:
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receiving a read or write operation signal; using the timing circuit, generating a sense trigger signal used to enable the plurality of sense amplifiers, wherein a timing of generation of the sense trigger signal is a function of at least a capacitive load associated with the at least one dummy bitline, and wherein the timing of generation of the sense trigger signal is independent of a capacitive load associated with a dummy wordline, and wherein each of the M dummy bitcells of the at least one dummy bitline includes pass gates that are negated such that none of the M dummy bitcells is selected using the dummy wordline. - View Dependent Claims (17, 18, 19, 20)
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Specification