Multi-memory device system and method for managing a lifetime thereof

• US 7,747,813 B2
• Filed: 09/07/2007
• Issued: 06/29/2010
• Est. Priority Date: 11/24/2006
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Primary Examiner(s): Song; Jasmine
• Application Number:
  US11/852,117
• Publication Number:
  US 20080126720A1
• Time in Patent Office: 1,026 Days
• Field of Search: 711/100, 711/103, 711/154, 711/161, 711/162, 711170-172
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

An apparatus, method, and computer program product are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect.

Claims

1. A method, comprising:

identifying at least one aspect associated with a lifetime of each of a plurality of memory device portions of at least one memory device;

determining by a controller coupled to a host processor and to the at least one memory device that the aspect associated with the lifetime of a first one of the memory device portions storing a first set of data exceeds that of the aspect associated with the lifetime of a second one of the memory device portions; and

in response to the determining, moving the first set of data from the first memory device portion to the second memory device portion;

wherein the first memory device portion and the second memory device portion are portions of a same one of the at least one memory device.

2. The method of claim 1, wherein the lifetime includes at least one of a desired lifetime, an actual lifetime, and an estimated lifetime.

3. The method of claim 1, wherein the at least one aspect includes at least one of a period of time, a rate of the operations that reduce the lifetime of at least one of the plurality of memory device portions, a total permitted number of the operations that reduce the lifetime of at least one of the plurality of memory device portions, and a duration of the lifetime.

4. The method of claim 1, wherein the at least one aspect indicates that the first set of data is more frequently overwritten with respect to a second set of data of the second memory device portion.

5. The method of claim 4, wherein the first set of data is moved from the first memory device portion to the second memory device portion, after a predetermined amount of time.

6. The method of claim 1, wherein the at least one memory device includes a mechanical storage device.

7. The method of claim 1, wherein the at least one memory devices includes a non-mechanical storage device.

8. The method of claim 1, wherein the at least one memory device includes a volatile memory device.

9. The method of claim 1, wherein the at least one memory device includes a nonvolatile memory device.

10. The method of claim 9, wherein the nonvolatile memory device includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, a multi-bit per cell NAND flash memory, a multi-level-multi-bit per cell NAND flash, and a large block flash memory.

11. The method of claim 1, wherein the at least one aspect comprises a frequency of writing.

12. The method of claim 1, further comprising:

receiving by the storage controller and from the host processor a command initiating an operation to be applied to the memory device portions;

determining by the storage controller if the operation is of a type that reduces the lifetime of the memory device portions; and

conditionally delaying at least a part of the operation based on the determining.

13. The method of claim 12, further comprising:

computing an estimated lifetime of the memory device portions based on the operation; and

comparing the estimated lifetime with a required lifetime;

wherein the conditionally delaying is further based on the comparing.

14. The method of claim 13, wherein the computing is based on an integral function including a rate of operations of the type that reduces the lifetime of the memory device portions.

15. The method of claim 14, wherein the aspect associated with the lifetime comprises the rate of operations of the type that reduces the lifetime of the memory device portions.

16. The method of claim 15, further comprising:

displaying, to a user of the memory device portions, the estimated lifetime.

17. The method of claim 16, wherein the displaying includes a graphical user interface.

18. An apparatus, comprising:

a controller enabled to identify at least one aspect associated with a lifetime of each of a plurality of memory device portions of at least one memory device, enabled to determine that the aspect associated with the lifetime of a first one of the memory device portions storing a first set of data exceeds that of the aspect associated with the lifetime of a second one of the memory device portions, and enabled to, in response to the determination whether the aspect associated with the lifetime of a first one of the memory device portions storing a first set of data exceeds that of the aspect associated with the lifetime of a second one of the memory device portions, move the first set of data from the first memory device portion to the second memory device portion;

wherein the first memory device portion and the second memory device portion are portions of a same one of the at least one memory device.

19. The apparatus of claim 18, wherein the controller is coupled between a host processor and the at least one memory device.