Method and system to construct a data-flow analyzer for a bytecode verifier

• US 7,757,223 B2
• Filed: 07/25/2005
• Issued: 07/13/2010
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Chauvel, Gerard, Lesot, Jean-Philippe, Peltier, Mikael
• Primary Examiner(s): Khatri; Anil
• Application Number:
  US11/188,502
• Publication Number:
  US 20060026404A1
• Time in Patent Office: 1,814 Days
• Field of Search: 717/134, 717/136, 717/137, 717154-160
• US Class Current: 717/155
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.

Claims

1. A processor, comprising:

a fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the processor; and

a decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions;

wherein the processor is configurable to execute the plurality of instructions and to verify that types of values exchanged between the plurality of instructions are correct,

wherein when the processor is configured to verify types of values, each instruction in the first native instruction set is associated with a micro-sequence configured to perform type verification corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the types of the values exchanged between the plurality of instructions are verified, and

when the processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction,

wherein a micro-sequence is one or more instructions from a second native instruction set of the processor.

2. The processor of claim 1,

wherein type verification corresponding to the instruction comprises:

reading a type indicator from a data structure; and

determining whether the type indicator is indicative of a type of a value that the instruction expects to read from the data structure when the instruction is executed.

3. The processor of claim 2, wherein an exception is generated when the type indicator read from the data structure is not indicative of an expected type.

4. The processor of claim 2, wherein the data structure is one selected from a group consisting of a stack and a local variable set.

5. The processor of claim 1, further comprising:

a vector table accessible by the decode logic, wherein the vector table comprises an entry for each instruction in the first native instruction set,

wherein when the processor is configured to verify types of values, the vector table is used to associate each instruction in the first native instruction set with the micro-sequence configured to perform type verification corresponding to the instruction, and

when the processor is configured to execute the plurality of instructions, the vector table is used to associate each instruction of the subset of instructions with the micro-sequence configured to perform the function of the instruction.

6. The processor of claim 5, wherein when a micro-sequence is associated with an instruction, the entry references a location in memory in which the micro-sequence is stored.

7. The processor of claim 1, wherein type verification corresponding to the instruction comprises writing a type indicator to a data structure, wherein the type indicator is indicative of a type of a value that the instruction would write to the data structure when the instruction is executed.

8. The processor of claim 7, wherein the data structure is one selected from a group consisting of a stack and a local variable set.

9. A method for verifying that types of values exchanged between a plurality of instructions from a first native instruction set of a processor are correct, comprising:

configuring the processor to verify types of values instead of executing instructions in the first native instruction set, wherein configuring comprises associating each instruction in the first native instruction set with a micro-sequence configured to perform type verification corresponding to the instruction;

responsive to fetching and decoding each instruction in the plurality of instructions, executing the micro-sequence associated with the instruction, wherein the types of the values exchanged between the plurality of instructions are verified; and

reconfiguring the processor to execute instructions in the first native instruction set after the types of the values are verified, wherein reconfiguring comprises associating each instruction in a subset of the first native instruction set with a micro-sequence configured to perform a function of the instruction, wherein all other instructions in the first native instruction set are executed directly by the processor,

wherein a micro-sequence is one or more instructions from a second native instruction set of the processor.

10. The method of claim 9, wherein

associating each instruction in the first native instruction set comprises placing a reference to the micro-sequence in an entry of a vector table, wherein the vector table comprises an entry for each instruction in the first native instruction set, and

fetching and decoding comprises accessing the vector table to locate the micro-sequence.

11. The method of claim 9, wherein type verification corresponding to the instruction comprises:

writing a type indicator to a data structure, wherein the type indicator is indicative of a type of a value that the instruction would write to the data structure when the instruction is executed.

12. The method of claim 9, wherein type verification corresponding to the instruction comprises:

reading a type indicator from a data structure; and

determining whether the type indicator is indicative of a type of a value that the instruction expects to read from the data structure when the instruction is executed.

13. The method of claim 12, further comprising generating an exception when the type indicator read from the data structure is not indicative of an expected type.

14. The method of claim 9, wherein type verification corresponding to the instruction comprises writing a type indicator to a data structure, wherein the type indicator is indicative of a type of a value that the instruction would write to the data structure when the instruction is executed.

15. A system, comprising:

a first processor; and

a second processor coupled to the first processor, the second processor comprising;

a fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the second processor; and

a decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions;

wherein the second processor is configurable to execute the plurality of instructions and to verify that types of values exchanged between the plurality of instructions are correct,

wherein when the second processor is configured to verify types of values, each instruction in the first native instruction set is associated with a micro-sequence configured to perform type verification corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the types of the values exchanged between the plurality of instructions are verified, and

when the second processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction,

wherein a micro-sequence is one or more instructions from a second native instruction set of the second processor.

16. The system of claim 15,

wherein type verification corresponding to the instruction comprises:

reading from a data structure a type indicator; and

determining whether the type indicator is indicative of a type of a value that the instruction would read from the data structure when executed.

17. The system of claim 16, wherein an exception is generated when the type indicator read from the data structure is not indicative of an expected type.

18. The system of claim 16, wherein the data structure is one selected from a group consisting of a stack and a local variable set.

19. The system of claim 15, wherein the second processor further comprises:

a vector table accessible by the decode logic, wherein the vector table comprises an entry for each instruction in the first native instruction set,

wherein when the second processor is configured to verify types of values, the vector table is used to associate each instruction in the first native instruction set with the micro-sequence configured to perform type verification corresponding to the instruction, and

wherein when the second processor is configured to execute the plurality of instructions, the vector table is used to associate each instruction of the subset of instructions with the micro-sequence configured to perform the function of the instruction.

20. The system of claim 19, wherein when a micro-sequence is associated with an instruction, the entry references a location in the memory in which the micro-sequence is stored.

21. The system of claim 15, wherein type verification corresponding to the instruction comprises writing a type indicator to a data structure, wherein the type indicator is indicative of a type of a value that the instruction would write to the data structure when the instruction is executed.

22. The system of claim 21, wherein the data structure is one selected from a group consisting of a stack and a local variable set.