3D R/W cell with reduced reverse leakage

• US 7,759,666 B2
• Filed: 06/29/2007
• Issued: 07/20/2010
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J., Kumar, Tanmay
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Valentine; Jami M
• Application Number:
  US11/819,989
• Publication Number:
  US 20090001347A1
• Time in Patent Office: 1,117 Days
• Field of Search: 257 1- 5, 438102-103, 365/202
• US Class Current: 257/2
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.

Claims

1. A nonvolatile memory device, comprising:

a semiconductor diode steering element;

a semiconductor read/write switching element; and

a C49 phase crystallization template layer which directly physically contacts the steering element, wherein the steering element is crystallized in direct contact with the C49 phase crystallization template layer.

2. The device of claim 1, further comprising at least one conductive layer located between the steering element and the read/write switching element.

3. The device of claim 2, wherein the at least one conductive layer comprises a titanium nitride layer.

4. The device of claim 2, wherein the steering element, the at least one conductive layer and the read/write switching element are arranged in series and together comprise a nonvolatile memory cell.

5. The device of claim 4, further comprising a first electrode and a second electrode electrically contacting the nonvolatile memory cell.

6. The device of claim 5, wherein the read/write switching element comprises a resistor.

7. The device of claim 6, wherein:

the read/write switching element comprises amorphous, polycrystalline or a combination amorphous and polycrystalline Group IV semiconductor resistor;

the steering element comprises a crystallized polycrystalline Group IV semiconductor diode; and

the at least one conductive layer contacts both the steering element and the read/write switching element.

8. The device of claim 7, wherein the C49 phase titanium silicide crystallization template layer contacts the steering element which comprises a polysilicon diode.

9. The device of claim 5, wherein the read/write switching element and the steering element are arranged in a pillar between the first electrode and the second electrode.

10. The device of claim 5, wherein in use, the read/write switching element of the memory cell switches from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied electrical pulse.

11. The device of claim 10, wherein steering element does not switch from the first resistivity state to the second resistivity state in response to the applied electrical pulse.

12. The device of claim 11, wherein the steering element is formed in a low resistivity state which does not change in response to the applied electrical pulse and the read/write switching element is formed in a high resistivity state which changes in response to the applied electrical pulse.

13. The device of claim 12, wherein an application of a second electrical pulse is adapted to switch the read/write switching element from the second resistivity state to the first resistivity state.

14. A nonvolatile memory device, comprising:

a crystallized polycrystalline silicon, germanium or silicon germanium semiconductor diode steering element;

a titanium silicide, titanium germanide or titanium silicide-germanide crystallization template layer having a C49 phase in physical contact with the diode steering element;

a semiconductor resistor read/write switching element;

at least one metal, metal silicide or titanium nitride conductive layer located between the steering element and the read/write switching element;

a first electrode electrically contacting the steering element; and

a second electrode electrically contacting the read/write switching element;

wherein the read/write switching element, the at least one conductive layer and the steering element are arranged in series in a pillar between the first electrode and the second electrode.

15. The device of claim 14, wherein:

the device comprises a monolithic three dimensional non-volatile memory device;

the read/write switching element comprises amorphous, polycrystalline or a combination amorphous and polycrystalline Group IV semiconductor resistor; and

the at least one conductive layer contacts the steering element and the read/write switching element.