Printed dopant layers

• US 7,767,520 B2
• Filed: 08/03/2007
• Issued: 08/03/2010
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Rockenberger, Joerg, Kamath, Arvind, Smith, Patrick, Zurcher, Fabio, Cleeves, James Montague
• Primary Examiner(s): Sarkar; Asok K
• Application Number:
  US11/888,949
• Publication Number:
  US 20080044964A1
• Time in Patent Office: 1,096 Days
• Field of Search: 257/E21.247, 438/191, 438/199, 438/249, 438/301, 438/558
• US Class Current: 438/249
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/3165 formed by oxidation H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Claims

1. A method for making a MOS transistor, comprising the steps of:

a) forming a plurality of semiconductor islands on an electrically functional substrate;

b) printing a first dielectric layer on or over a first subset of said semiconductor islands and a second dielectric layer on or over a second subset of said semiconductor islands, said first dielectric layer containing a first dopant and said second dielectric layer containing a second dopant different from said first dopant, such that said first and second dielectric layers are laterally adjacent to each other and do not overlap each other over the active region of said MOS transistor; and

c) annealing said dielectric layer(s), said semiconductor islands and said substrate sufficiently to diffuse said first dopant into said first subset of semiconductor islands and said second dopant into said second subset of semiconductor islands.

2. The method of claim 1, wherein each of said semiconductor islands comprises a Group IVA element.

3. The method of claim 2, wherein said Group IVA element comprises silicon.

4. The method of claim 1, wherein forming said plurality of semiconductor islands comprises printing a semiconductor ink.

5. The method of claim 4, wherein said semiconductor ink comprises a silane in an amount of from 1 to 50 wt. % of said ink and a solvent in which said silane is soluble.

6. The method of claim 5, wherein said silane has a formula Si_xH_y, where x is from 3 to 1000, and y is from x to (2x+2), where x may be derived from an average number molecular weight of said silane.

7. The method of claim 4, wherein said semiconductor ink is printed in a pattern forming an array of said semiconductor islands, said first dielectric layer is printed on or over a first group of adjacent semiconductor islands, and said second dielectric layer is printed on or over a second group of adjacent semiconductor islands.

8. The method of claim 1, further comprising forming a gate dielectric layer on or over at least a subset of said plurality of semiconductor islands.

9. The method of claim 8, further comprising forming a gate on each of the gate dielectric layers.

10. The method of claim 9, wherein forming said gate comprises printing a gate precursor ink on the gate dielectric layer.

11. The method of claim 9, further comprising, prior to printing the first and second dielectric layers, removing an exposed portion of said gate dielectric layer.

12. The method of claim 10, wherein said gate precursor ink comprises a metal-containing material, and said metal-containing material comprises metal nanoparticles.

13. The method of claim 1, wherein the method comprises printing the first and second dielectric layers, such that the first and second dielectric layers overlap.

14. The method of claim 1, wherein said annealing is conducted at a temperature and for a length of time sufficient to form source/drain terminals.

15. The method of claim 1, further comprising, after printing the first dielectric layer and the second dielectric layer, forming contact holes in said first dielectric layer and in said second dielectric layer, exposing (i) at least part of an upper surface of the gate and (ii) portions of the semiconductor island on opposed sides of the at least partially exposed gate.

16. The method of claim 15, further comprising forming a metal layer in contact with said upper surface of each gate and with each exposed portion of said semiconductor islands.

17. The method of claim 16, wherein forming said metal layer comprises printing a metal ink on the first and second dielectric layers and the exposed surfaces of the gate and the semiconductor islands.

18. A method for making a MOS transistor, comprising the steps of:

a) forming a plurality of transistor gates on or over a substrate;

b) printing a first dielectric layer on or over a first subset of said transistor gates and a second dielectric layer on or over a second subset of said transistor gates, said first dielectric layer containing a first dopant and said second dielectric layer containing a second dopant different from said first dopant, such that said first and second dielectric layers are laterally adjacent to each other and do not overlap each other over the active region of said MOS transistor;

c) forming contact holes in each of said first and second dielectric layers, exposing an upper surface of each transistor gate; and

d) etching the first and second dielectric layers sufficiently to widen said contact holes.

19. The method of claim 18, further comprising, prior to forming the plurality of transistor gates, printing semiconductor islands or layers on the substrate, wherein the first dielectric layer is printed at least in part on a first subset of the semiconductor islands or layers, and the second dielectric layer is printed at least in part on a second subset of the semiconductor islands or layers.

20. The method of claim 18, further comprising annealing said dielectric layer(s) and said semiconductor islands or layers sufficiently to diffuse said first dopant into a first subset of semiconductor islands or layers and said second dopant into a second subset of semiconductor islands or layers.

21. The method of claim 18, further comprising printing a siliconand/or metal-containing ink in the contact holes.

22. The method of claim 18, wherein forming contact holes comprises removing portions of said first dielectric layer and said second dielectric layer.

23. The method of claim 18, wherein printing the first and second dielectric layers further comprises forming said contact holes.