Integrated circuit with multidimensional switch topology

• US 7,768,314 B2
• Filed: 03/28/2005
• Issued: 08/03/2010
• Est. Priority Date: 05/12/2004
• Status: Expired due to Fees

• Current Assignee: National University Corporation Okayama University
• Original Assignee: National University Corporation Okayama University
• Inventors: Matsumoto, Yohei, Masaki, Akira
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/596,011
• Publication Number:
  US 20090009215A1
• Time in Patent Office: 1,954 Days
• Field of Search: 326/47, 326/101, 326/82, 326/83, 716 12- 14, 716/17
• US Class Current: 326/101
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.

Claims

1. A method of designing an FPGA, comprising embedding an interconnected n-dimensional FPGA switch topology in an m-dimensional integrated circuit, where m and n are natural numbers, m<

n, and 4≦

n.

2. The method of claim 1, wherein m=2 and n=4.

3. A semiconductor integrated circuit, comprising an FPGA including an interconnected n-dimensional FPGA switch topology embedded in an m-dimensional integrated circuit, where m and n are natural numbers, m<

n, and 4≦

n.

4. The semiconductor integrated circuit of claim 3, wherein m=2 and n=4.

5. The semiconductor integrated circuit of claim 3, wherein in the FPGA, wire channels in axial directions associated with the m dimensions include wires of various lengths.

6. The semiconductor integrated circuit of claim 3, wherein in the FPGA, wire channels in axial directions associated with the m dimensions include wires of full length.

7. The semiconductor integrated circuit of claim 3, wherein in the FPGA, closely located wire channels in axial directions associated with the m dimensions have ends connected to one another.

8. The semiconductor integrated circuit of claim 3, wherein in the FPGA, each basic block has a hierarchical structure.

10. The semiconductor integrated circuit of claim 4, wherein in the FPGA:

basic blocks located at the same u-v position are constructed in a 2-dimensional array as a single subregion;

connections are made in an x-direction between basic blocks adjoining in a lateral direction;

connections are made in a y-direction between basic blocks adjoining in a longitudinal direction;

the subregions are arranged in a 2-dimensional array;

connections are made in a u-direction between basic blocks located at the same x-y position in subregions adjoining in the lateral direction; and

connections are made in a v-direction between basic blocks located at the same x-y position in subregions adjoining in the longitudinal direction.

12. The semiconductor integrated circuit of claim 10, wherein in the FPGA, wire channels in the y-direction in a first subregion each have a lower end connected to an upper end of one of wire channels in the y-direction in a second subregion which is immediately below the first subregion.

13. The semiconductor integrated circuit of claim 10, wherein in the FPGA, wire channels in the x-direction in a first subregion each have a right hand end connected to a left hand end of one of wire channels in the x-direction in a second subregion which is immediately to the right of the first subregion.

9. A semiconductor integrated circuit, comprising an FPGA including a 3-dimensional FPGA switch topology embedded in a 2-dimensional integrated circuit,

wherein in the FPGA:

basic blocks located at the same x-y position are constructed 2-dimensionally as a single subregion;

connections are made in a z-direction;

the subregions are arranged in a 2-dimensional array;

connections are made in an x-direction between basic blocks located at the same z position in subregions adjoining in a lateral direction; and

connections are made in a y-direction between basic blocks located at the same z position in subregions adjoining in a longitudinal direction, wherein in each subregion in the FPGA, wire channels in the z-direction each have a lower end and an upper end connected to each other.

11. The semiconductor integrated circuit of claim 9, wherein in the FPGA, the subregions are arranged 2-dimensionally so that basic blocks adjoining in the z-direction adjoin each other.

14. The semiconductor integrated circuit of claim 11, wherein in the FPGA, the subregions are constructed by arranging the basic blocks linearly in the longitudinal direction.

15. The semiconductor integrated circuit of claim 11, wherein in the FPGA, the subregions are constructed by folding a z-axis at least once to arrange the basic blocks.

16. The semiconductor integrated circuit of claim 14, wherein in the FPGA, wire channels in the z-direction in a first subregion each have a lower end connected to an upper end of one of wire channels in the z-direction in a second subregion which is immediately below the first subregion.

21. The semiconductor integrated circuit of claim 9, wherein the wire channels in the z-direction are connected to each other at their ends to form a loop.

17. A programmable device, comprising:

basic blocks; and

switching elements provided to the basic blocks, the basic blocks being connected to one another via the associated switching elements,

wherein;

at least some of the basic blocks are arranged in a matrix and constitute basic block matrices in which those particular basic blocks are sequentially connected in rows and columns;

basic blocks located at corresponding matrix positions in the basic block matrices are connected to one another;

the basic block matrices are arranged in a plane;

basic blocks located at corresponding matrix positions in the basic block matrices are located together in a predetermined area; and

the programmable device includes an n-dimensional switch topology in an m-dimensional integrated circuit, where m and n are natural numbers, m<

n, and 4≦

n.

18. The programmable device of claim 17, wherein basic blocks located at corresponding matrix positions in the basic block matrices are connected 1-dimensionally to each other.

19. A programmable device, comprising:

basic blocks; and

switching elements provided to the basic blocks, the basic blocks being connected to one another via the associated switching elements,

wherein;

at least some of the basic blocks are arranged in a matrix and constitute basic block matrices in which those particular basic blocks are sequentially connected in rows and columns;

basic blocks located at corresponding matrix positions in the basic block matrices are connected to one another;

the basic block matrices are arranged in a plane;

basic blocks located at corresponding matrix positions in the basic block matrices are connected 2-dimensionally to one another; and

the programmable device includes an n-dimensional switch topology in an m-dimensional integrated circuit, where m and n are natural numbers, m<

n, and 4≦

n.

20. The programmable device of claim 19, wherein those basic blocks which constitute the basic block matrices are located together in a predetermined area.