Controlling electromechanical behavior of structures within a microelectromechanical systems device

• US 7,781,850 B2
• Filed: 03/25/2005
• Issued: 08/24/2010
• Est. Priority Date: 09/20/2002
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Batey, John, Chui, Clarence, Miles, Mark W., Kothari, Manish, Tung, Ming-Hau
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): Diaz; Jose R
• Application Number:
  US11/090,911
• Publication Number:
  US 20050250235A1
• Time in Patent Office: 1,978 Days
• Field of Search: 257/414, 257/428, 257/437
• US Class Current: 257/414
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2201/053 Depositing a protective layers
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26

Abstract

In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Claims

1. A MEMS device having a substrate comprising:

an electrode layer formed over the substrate;

a dielectric layer formed over the electrode layer, wherein the dielectric layer comprises silicon oxide;

a first etch barrier layer formed over the dielectric layer;

a cavity located above the first etch barrier;

a moving layer located above the cavity; and

a fourth layer formed between the electrode layer and the first dielectric layer, said fourth layer comprising aluminum oxide.

2. The device of claim 1, wherein the first etch barrier layer comprises aluminum oxide.

3. The device of claim 1, wherein the device is an interferometric modulator.

4. The device of claim 1, additionally comprising a second etch barrier layer formed over the first etch barrier layer.

5. The device of claim 4, wherein the second etch barrier layer comprises silicon oxide.

6. The device of claim 4, wherein the second etch barrier layer comprises silicon nitride.

7. The device of claim 4, wherein the second etch barrier layer comprises titanium.

8. The device of claim 4, wherein the second etch barrier layer comprises molybdenum.

9. The device of claim 4, wherein the second etch barrier layer comprises amorphous silicon.

10. The device of claim 4, wherein the second etch barrier layer has a varying thickness over the surface of the first etch barrier layer.

11. The device of claim 10, wherein the second etch barrier covers only a portion of the first etch barrier layer.