Configurable ports for a host ethernet adapter

• US 7,782,888 B2
• Filed: 12/10/2007
• Issued: 08/24/2010
• Est. Priority Date: 04/01/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Vaidhyanathan, Natarajan, Chang, Chih-jen, Damon, Philippe, Calvignac, Jean Louis, Verplanken, Fabrice Jean, Basso, Claude, Verrilli, Colin B.
• Primary Examiner(s): Ton; Dang T
• Assistant Examiner(s): LEE, KEVIN H
• Application Number:
  US11/953,820
• Publication Number:
  US 20080089358A1
• Time in Patent Office: 988 Days
• Field of Search: 370/366, 370/367, 370/419, 370/236
• US Class Current: 370/419
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC

Abstract

A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.

Claims

1. An Ethernet adapter comprising:

a plurality of layers for receiving and transmitting packets from and to a processor;

wherein the plurality of layers include a common high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.

2. The Ethernet adapter of claim 1 wherein the different speed data sources comprise a 10 Gigabit (G) source and a plurality of 1 G sources.

3. The Ethernet adapter of claim 1 wherein the high speed serdes comprises:

a receive section for receiving data from a data source;

a transmit section for transmitting data to a data source; and

a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.

4. The Ethernet adapter of claim 3 wherein the receive section and transmit section share a plurality of lanes.

5. The Ethernet adapter of claim 1 wherein the reference clock speed is 156.25 MHz, and wherein the different modes of operation comprise a 10 G XFI mode using a phase locked loop multiplication ratio of 66 and no data repetition, a 10 G XAUI mode using a phase locked loop multiplication ratio of 40 and data repetition at bit level with each bit being repeated two times, and a 1 G SGMII mode using a phase locked loop multiplication ratio of 64 and data repetition at bit level with each bit being repeated eight times.

6. The Ethernet adapter of claim 1 wherein the high speed serdes includes a mechanism to provide to the layers dedicated to each media speed, receive companion clocks and transmit companion clocks running at the frequency at which the serdes would have run if it was operating at media speed.

7. The Ethernet adapter of claim 3 wherein the PLL controls the internal clock rate by setting different multiplication ratios for each of the different modes of operation.

25. The Ethernet adapter of claim 1, wherein one or more of the different modes does not use data repetition.

8. A network interface controller (NIC) comprising:

an interface to a private bus of a processor; and

an Ethernet adapter coupled to the interface;

the Ethernet adapter comprising a plurality of layers for receiving and transmitting packets from and to the processor;

wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.

9. The NIC of claim 8 wherein the different speed data sources comprise a 10 Gigabit (G) source and a plurality of 1 G sources.

10. The NIC of claim 8 wherein the high speed serdes comprises:

a receive section for receiving data from a data source;

a transmit section for transmitting data to a data source; and

a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.

11. The NIC of claim 10 wherein the receive section and transmit section share a plurality of lanes.

12. The NIC of claim 8 wherein the reference clock speed is 156.25 MHz, and wherein the different modes of operation comprise a 10 G XFI mode using a phase locked loop multiplication ratio of 66 and no data repetition, a 10 G XAUI mode using a phase locked loop multiplication ratio of 40 and data repetition at bit level with each bit being repeated two times, and a 1 G SGMII mode using a phase locked loop multiplication ratio of 64 and data repetition at bit level with each bit being repeated eight times.

13. The NIC of claim 10 wherein the PLL controls the internal clock rate by setting different multiplication ratios for each of the different modes of operation.

14. The NIC of claim 8 wherein the high speed serdes includes a mechanism to provide to the layers dedicated to each media speed, receive companion clocks and transmit companion clocks running at the frequency at which the serdes would have run if it was operating at media speed.

15. A server comprising:

a processor;

the processor including a private bus; and

a network interface controller (NIC) coupled to the private bus, the NIC including an Ethernet adapter;

the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to the processor;

wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.

16. A method for an Ethernet adapter, the Ethernet adapter including a plurality of layers;

the method comprising;

utilizing the plurality of layers to receive and transmit packets from and to a processor;

receiving data from and providing data to different speed data sources on the same pins of the Ethernet adapter; and

allowing the configuration of the plurality of layers to different modes of operation;

wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.

17. The method of claim 16 wherein allowing the configuration is provided by configuring a common high speed serializer/deserializer (high speed serdes) included within the plurality of layers.

18. The method of claim 16 wherein the different speed data sources comprise a 10Gigabit (G) source and a plurality of 1 G sources.

19. The method of claim 17 wherein the high speed serdes comprises:

a receive section for receiving data from a data source;

a transmit section for transmitting data to a data source; and

a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.

20. The method of claim 19 wherein the receive section and transmit section share a plurality of lanes.

21. The method of claim 16 wherein the high speed serdes includes a mechanism to provide to the layers dedicated to each media speed, receive companion clocks and transmit companion clocks running at the frequency at which the serdes would have run if it was operating at media speed.

22. The method of claim 16 wherein the reference clock speed is 156.25 MHz, and wherein the different modes of operation comprise a 10 G XFI mode using a phase locked loop multiplication ratio of 66 and no data repetition, a 10 G XAUI mode using a phase locked loop multiplication ratio of 40 and data repetition at bit level with each bit being repeated two times, a 1 G SGMII mode using a phase locked loop multiplication ratio of 64 and data repetition at bit level with each bit being repeated eight times.

23. The method of claim 19 wherein the PLL controls an internal clock rate by setting different multiplication ratios for each of the different modes of operation.

24. The method of claim 19, further comprising:

the transmit section transmitting data with the repeated bits back-to-back; and

the receive section receiving data with the repeated bits back-to-back and capturing only one of the repeated bits.