Interleaved voltage controlled oscillator

• US 7,786,813 B2
• Filed: 04/07/2008
• Issued: 08/31/2010
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Qi, Jieming, Hailu, Eskinder, Boerstler, David W., Shen, Mike
• Primary Examiner(s): Chang; Joseph
• Assistant Examiner(s): SHIN, JEFFREY M
• Application Number:
  US12/098,490
• Publication Number:
  US 20080186104A1
• Time in Patent Office: 876 Days
• Field of Search: 331/57, 331/176, 331/185, 331/186
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

Claims

1. A data processing system comprising a central processing unit (CPU), operable to generate a clock signal, the CPU having an interleaved voltage-controlled oscillator (VCO) comprising:

a ring circuit comprising a series connection of main logic inverter gates;

a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates;

wherein each delay element comprises;

a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and

a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate;

at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistor, the field effect transistors responsive to a compensating voltage input that is proportional to temperature;

an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature;

an amplifier in connection with the electronic circuit to amplify the voltage signal;

a DC offset generator configured to adjust the amplified voltage signal, thereby providing the compensating voltage input;

a random access memory (RAM) configured to store operating commands;

a read only memory (ROM) configured to store BIOS and recovery code; and

an I/O adapter, and a bus system coupling the CPU to the ROM, the I/O adapter, and the RAM.

2. The system of claim 1, wherein:

the electronic circuit provides a voltage signal directly proportional to temperature.

3. The system of claim 1, wherein:

the temperature compensation circuit is in parallel connection to the delay element.

4. The system of claim 1, wherein:

the temperature compensation circuit is in parallel connection to at least one of the main logic inverter gates.

5. The system of claim 1, wherein:

the VCO comprises components manufactured with 65 nanometer (nm) technology employing a lithographic mode of manufacture.

6. The system of claim 1, wherein:

the electronic circuit is configured to provide a voltage change responsive to temperature of approximately 1000 parts per million per degree Celsius.

7. The system of claim 1, wherein:

the amplifier and DC offset generator are configured to provide the compensating voltage input that varies from about 0.6 volts (V) at 5 degrees Celsius to about 1.1V at 85 degrees Celsius.