Mixed-mode PLL
First Claim
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1. A mixed-mode PLL, comprising:
- an analog phase correction path comprising a linear phase correction unit (LPCU); and
a digital frequency correction path comprising a digital integral path circuit,wherein the digital frequency correction path tracks frequency of a reference clock in a digital domain and the linear phase correction unit generates a phase error signal to change a phase of an output of the digital frequency correction path.
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Abstract
A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.
26 Citations
20 Claims
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1. A mixed-mode PLL, comprising:
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an analog phase correction path comprising a linear phase correction unit (LPCU); and a digital frequency correction path comprising a digital integral path circuit, wherein the digital frequency correction path tracks frequency of a reference clock in a digital domain and the linear phase correction unit generates a phase error signal to change a phase of an output of the digital frequency correction path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A linear phase correction unit (LPCU) for a phase locked loop (PLL), comprising:
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a bias circuit; a varactor having two ends thereof coupled to the bias circuit; and a current source circuit dynamically providing a pull-up current or a pull-down current to the bias circuit. - View Dependent Claims (16)
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17. A linear phase correction unit (LPCU) for a phase locked loop (PLL), comprising:
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first and second bias circuits; a varactor having two ends thereof respectively coupled to the first and second bias circuits; and first and second current source circuits dynamically providing a pull-up current or a pull-down current respectively to the first and second bias circuits. - View Dependent Claims (18, 19)
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20. A linear phase correction unit (LPCU) for a phase locked loop (PLL), comprising:
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a varactor having two ends, wherein one and the other ends of the varactor are respectively controlled by a phase up signal and a phase down signal of a phase frequency detector (PFD).
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Specification