TFT array panel having a first pixel region having first transmissive with first and third reflective electrodes and a second pixel region having second transmissive with second and fourth reflective electrodes where the area ratios of the first and third reflective electrodes to the second and fourth reflective electrodes are different

• US 7,791,692 B2
• Filed: 06/02/2006
• Issued: 09/07/2010
• Est. Priority Date: 06/27/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Mun-Pyo, Yang, Young-Chol, Choi, Jeong-Ye, Kim, Sang-Il
• Primary Examiner(s): HEYMAN, JOHN S
• Application Number:
  US11/445,817
• Publication Number:
  US 20060290848A1
• Time in Patent Office: 1,558 Days
• Field of Search: 349/114, 349/117, 349/109
• US Class Current: 349/114
• CPC Class Codes: G02F 1/133555 Transflectors
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 2201/52 RGB geometrical arrangements
• CPC Class Codes: G09G 2300/0456 with a reflective area and a transmissive area combined in one pixel, such as in transflectance pixels
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

The present invention provides a thin film transistor (“TFT”) array panel including a substrate, first and second transmissive electrodes formed on the substrate, first and second reflective electrodes connected to the first and second transmissive electrodes, respectively, and third and fourth reflective electrodes separated from the first and second transmissive electrodes and the first and second reflective electrodes. A first area ratio of the first and third reflective electrodes is different from a second area ratio of the second and fourth reflective electrodes. A liquid crystal display (“LCD”) includes the TFT array panel, and a method is provided for coinciding voltage-reflection curves of adjacent pixels in the LCD.

Claims

1. A thin film transistor array panel, comprising:

a substrate;

first and second transmissive electrodes formed on the substrate;

first and second reflective electrodes connected to the first and second transmissive electrodes, respectively; and

third and fourth reflective electrodes separated from the first and second transmissive electrodes and the first and second reflective electrodes,

wherein a first area ratio of the first reflective electrode to the third reflective electrode is different from a second area ratio of the second reflective electrode to the fourth reflective electrode, and

the first transmissive electrode, the first reflective electrode and the third reflective electrode are disposed within a first pixel region, and the second transmissive electrode, the second reflective electrode, and the fourth reflective electrode are disposed within a second pixel region.

2. The thin film transistor array panel of claim 1, wherein a total size of the first and third reflective electrodes is substantially equal to a total size of the second and fourth reflective electrodes.

3. The thin film transistor array panel of claim 1, further comprising:

a third transmissive electrode formed on the substrate;

a fifth reflective electrode connected to the third transmissive electrode; and

a sixth reflective electrode separated from the third transmissive electrode and the fifth reflective electrode,

wherein a third area ratio of the fifth reflective electrode to the sixth reflective electrode is different from the first area ratio and the second area ratio, and

the third transmissive electrode, the fifth reflective electrode and the sixth reflective electrode are disposed within a third pixel region.

4. The thin film transistor array panel of claim 3, wherein a total size of the fifth and sixth reflective electrodes is substantially equal to a total size of the first and third reflective electrodes and a total size of the second and fourth reflective electrodes.

5. The thin film transistor array panel of claim 1, wherein at least one of the transmissive electrodes, the first reflective electrode, and a first conductor connected to the transmissive electrodes and the first reflective electrode overlaps the third reflective electrode or a second conductor connected to the third reflective electrode.

6. The thin film transistor array panel of claim 5, further comprising an insulating layer formed between the first transmissive electrodes and the third reflective electrode and between the second transmissive electrode and the fourth reflective electrode.

7. The thin film transistor array panel of claim 5, further comprising a first insulating layer formed between the first and second conductors overlapping each other.

8. The thin film transistor array panel of claim 7, further comprising a second insulating layer formed between the first and third reflective electrodes and the first conductor.

9. The thin film transistor array panel of claim 5, further comprising an insulating layer formed between the first and third reflective electrodes overlapping each other.

10. The thin film transistor array panel of claim 1, wherein a data voltage is applied to the first and second reflective electrodes, and a voltage lower than the data voltage is applied to the third and fourth reflective electrodes.

11. The thin film transistor array panel of claim 1, wherein a cell gap of the thin film transistor array panel in a transmissive region and in a reflective region is substantially same.