Micropump for integrated device for biological analyses

• US 7,794,611 B2
• Filed: 01/24/2008
• Issued: 09/14/2010
• Est. Priority Date: 09/17/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Scurati, Mario
• Primary Examiner(s): CULBERT, ROBERTS P
• Application Number:
  US12/019,630
• Publication Number:
  US 20080138210A1
• Time in Patent Office: 964 Days
• Field of Search: 216/2, 422/100, 438/694, 438/800
• US Class Current: 216/2
• CPC Class Codes: B01L 2300/0816 Cards, e.g. flat sample carriers usually with flow in two horizontal directions
• CPC Class Codes: B01L 2300/1827 using resistive heater
• CPC Class Codes: B01L 2400/049 vacuum
• CPC Class Codes: B01L 2400/0677 phase change valves; Meltable, freezing, dissolvable plugs; Destructible barriers
• CPC Class Codes: B01L 3/50273 characterised by the means or forces applied to move the fluids micropumps F04B19/006, of the membrane type F04B43/043
• CPC Class Codes: B01L 7/52 with provision for submitting samples to a predetermined sequence of different temperatures, e.g. for treating nucleic acid samples amplification or hybridisation processes per se C12Q1/68; controlling sequential reactions for synthesis B01J19/0046
• CPC Class Codes: F04B 43/043 Micropumps

Abstract

A micropump includes a body (10) of semiconductor material, accommodating fluid-tight chambers (32), having an internal preset pressure, lower than atmospheric pressure. The fluid-tight chambers (32), sealed by a diaphragm (35) that can be electrically opened, are selectively openable using a first electrode (37) and second electrodes (38), accommodating between them portions of the diaphragm (35).

Claims

1. A process for manufacturing a vacuum micropump, comprising the steps of:

a) forming cavities in a substrate of a wafer of semiconductor material; and

b) sealing said cavities at a preset pressure,

wherein said step of forming cavities comprises the steps of;

i) forming, on top of said substrate, a mask having sets of openings;

ii) etching said substrate through said sets of openings;

iii) coating exposed portions of said mask with a first layer of said semiconductor material; and

iv) thermally oxidizing said first layer so as to close said first sets of openings.

2. The process according to claim 1, comprising the steps of:

a) growing an epitaxial layer on said mask;

b) depositing at least one conductive line on top of said epitaxial layer; and

c) etching said conductive line and said epitaxial layer until said cavities are reached.

3. The process according to claim 1, wherein said step of sealing comprises depositing a second layer of dielectric material at controlled pressure.

4. The process according to claim 3, wherein said second layer is of silicon dioxide.

5. The process according to claim 4, in which said second layer has a thickness not greater than 1 μ

m.