Trench depth monitor for semiconductor manufacturing

• US 7,795,045 B2
• Filed: 02/13/2009
• Issued: 09/14/2010
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: IceMOS Technology Ltd
• Original Assignee: IceMOS Technology Ltd
• Inventors: Ishiguro, Takeshi, Sugiura, Kenji, Griffin, Hugh J.
• Primary Examiner(s): Lindsay, Jr.; Walter L
• Assistant Examiner(s): Pompey; Ron
• Application Number:
  US12/371,021
• Publication Number:
  US 20090200547A1
• Time in Patent Office: 578 Days
• Field of Search: 438/8, 438/9, 438/14, 438/16, 257/E21.526, 257/E21.528, 257/E21.546, 257/E21.577
• US Class Current: 438/9
• CPC Class Codes: B81B 2203/033 Trenches
• CPC Class Codes: B81C 1/00619 Forming high aspect ratio structures having deep steep walls
• CPC Class Codes: B81C 2201/0138 Monitoring physical parameters in the etching chamber, e.g. pressure, temperature or gas composition
• CPC Class Codes: B81C 99/0065 Process control; Yield prediction
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate and determining an etch ratio. The least one device trench and at least one monitor trench are simultaneously formed in the first main surface of the semiconductor material layer. The at least one monitor trench is monitored to detect when it extends to a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio.

Claims

1. A method of manufacturing a semiconductor wafer having at least one device trench, the at least one device trench having a first depth position, the method comprising:

(a) providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer disposed on the first main surface of the semiconductor substrate, the semiconductor material layer having first and second main surfaces;

(b) pre-determining an etch ratio by

(i) forming, in a test wafer, at least one first trench having a first width and at least one second trench having a second width, the first and second widths being different, and

(ii) measuring a first depth of the at least one first trench and a second depth of the at least one second trench to thereby calculate the etch ratio based on the first and second widths;

(c) simultaneously forming in the semiconductor substrate

(i) the at least one device trench from the first main surface of the semiconductor material layer, the at least one device trench having the first width, and

(ii) at least one monitor trench from the first main surface of the semiconductor material layer;

the at least one monitor trench having the second width, and

(d) detecting with an optical profiler whether the at least one monitor trench extends to a second depth position, a ratio of the first depth position to the second depth position being generally equal to the etch ratio.

2. The method of claim 1, wherein the second width is greater than the first width.

3. The method of claim 1, further comprising:

(e) forming at least one die on the semiconductor wafer; and

(f) forming at least one process control module (PCM) on the semiconductor wafer.

4. The method of claim 3, further comprising:

(g) forming the at least one device trench in the at least one die; and

(h) forming the at least one monitor trench in the PCM.

5. The method of claim 1, further comprising:

(e) when detection indicates that the at least one monitor trench extends to a depth less than the second depth position, repeating steps (c) and (d).

6. The method of claim 1, wherein the first width is greater than the second width.

7. The method of claim 1, wherein the at least one device trench and the at least one monitor trench are formed by the same process.

8. The method of claim 1, wherein the steps (a)-(d) are performed sequentially.

9. The method of claim 1, wherein prior to commencement of each of the steps (a)-(d), the respective preceding step is substantially completed.

10. The method of claim 1, wherein prior to commencement of each of the steps (a)-(d), the respective preceding step is fully completed.

11. The method of claim 1, wherein the first depth position extends to the first main surface of the semiconductor substrate.

12. A method of manufacturing a semiconductor wafer having at least one device trench, the at least one device trench having a first depth position comprising:

(a) providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer disposed on the first main surface of the semiconductor substrate, the semiconductor material layer having first and second main surfaces;

(b) pre-determining an etch ratio by

(i) forming, in a test wafer, at least one first trench having a first width and at least one second trench having a second width, the first and second widths being different, and

(ii) measuring a first depth of the at least one first trench and a second depth of the at least one second trench to thereby calculate the etch ratio based on the first and second widths;

(c) simultaneously forming in the semiconductor substrate

(i) the at least one device trench from the first main surface of the semiconductor material layer, the at least one device trench having the first width, and

(ii) at least one monitor trench from the first main surface of the semiconductor material layer, the at least one monitor trench having the second width;

(d) monitoring a depth of the at least one monitor trench using an optical profiler; and

(e) ceasing formation of the at least one device trench and the at least one monitor trench upon attainment by the at least one monitor trench of a second depth position, a ratio of the first depth position to the second depth position being generally equal to the etch ratio.

13. The method of claim 12, wherein the second width is greater than the first width.

14. The method of claim 12, further comprising:

(f) forming at least one die on the semiconductor wafer; and

(g) forming at least one process control module (PCM) on the semiconductor wafer.

15. The method of claim 14, further comprising:

(h) forming the at least one device trench in the at least one die; and

(i) forming the at least one monitor trench in the PCM.

16. The method of claim 12, wherein the first width is greater than the second width.

17. The method of claim 12, wherein the at least one device trench and the at least one monitor trench are formed by the same process.

18. The method of claim 12, wherein the steps (a)-(e) are performed sequentially.

19. The method of claim 12, wherein prior to commencement of each of the steps (a)-(e), the respective preceding step is substantially completed.

20. The method of claim 12, wherein prior to commencement of each of the steps (a)-(e), the respective preceding step is fully completed.

21. The method of claim 12, wherein the first depth position extends to the first main surface of the semiconductor substrate.

22. A method of manufacturing a semiconductor wafer having at least one device trench, the at least one device trench having a first depth position, the method comprising:

(a) providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer disposed on the first main surface of the semiconductor substrate, the semiconductor material layer having first and second main surfaces;

(b) pre-determining an etch ratio by

(i) forming, in a test wafer, at least one first trench having a first width and at least one second trench having a second width, the first and second widths being different, and

(ii) measuring a first depth of the at least one first trench and a second depth of the at least one second trench to thereby calculate the etch ratio based on the first and second widths;

(c) simultaneously forming in the semiconductor substrate

(i) the at least one device trench from the first main surface of the semiconductor material layer, the at least one device trench having the first width, and

(ii) at least one monitor trench from the first main surface of the semiconductor material layer, the at least one monitor trench having the second width; and

(d) detecting with an optical profiler whether the at least one monitor trench extends to a second depth position, a ratio of the first depth position to the second depth position being generally proportional to the etch ratio.