Method for generating timing data packet

• US 7,797,685 B2
• Filed: 05/16/2006
• Issued: 09/14/2010
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Agarwala, Manisha, Johnsen, John M., Thome, Bryan
• Primary Examiner(s): DAS, CHAMELI
• Application Number:
  US11/383,540
• Publication Number:
  US 20060255985A1
• Time in Patent Office: 1,582 Days
• Field of Search: 717125-131, 714/814, 714/744
• US Class Current: 717/128
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program

Abstract

During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log information. The various streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. After data corruption a sync point is inserted into the data stream. The ID of this sync point may repeat a previous sync point ID.

Claims

1. A method of generating timing data packets comprising the steps of:

generating a normal timing data packet having a fixed length by

generating a predetermined number of leading bits having a first pattern, and

generating remaining bits of said normal timing data packet wherein each bit corresponds to an operational cycle, each bit having a first digital state indicating said corresponding operational cycle is an active cycle and a second digital state opposite to said first digital state indicating said corresponding operational cycle is a stall cycle; and

generating an alternate timing data packet having said fixed length by

generating said predetermined number of leading bits having a second pattern different from said first pattern indicating an alternate timing packet, and

generating remaining bits of said alternate timing data packet encoding additional information.

2. The method of claim 1, wherein:

said step of generating remaining bits of said alternate timing data packet generates bits representing a recurring status pattern.

3. The method of claim 2, wherein:

said step of generating remaining bits of said alternate timing data packet further generates bits representing a number of times said status pattern occurs.

4. The method of claim 1, wherein:

said step of generating remaining bits of said alternate timing data packet generates bits representing additional control functions.

5. The method of claim 1, wherein:

said fixed length consists of 10 bits;

said predetermined number of leading bits consists of 2 bits; and

said remaining bits consists of 8 bits.

6. The method of claim 5, wherein:

said first pattern consists of “

11”

.

7. The method of claim 5, wherein:

said second pattern consists of “

10”

.

8. The method of claim 1, wherein:

said first digital state consists of “

0”

.

9. The method of claim 1, wherein:

said second digital state consists of “

1”

.