NAND mobile devices capable of updating firmware or software in a manner analogous to NOR mobile devices
First Claim
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1. A mobile electronic device having a plurality of processors, each processor having its own address space, the mobile electronic device comprising:
- a plurality of NAND memory units communicatively coupled to and associated with the plurality of processors in one-to-one correspondence;
an update agent executable on one of the plurality of processors, the update agent capable of updating code in the NAND memory unit corresponding to the one of the plurality of processors;
an update package resident in the NAND memory unit corresponding to the one of the plurality of processors;
the update agent employing the update package to update the code;
a plurality of random access memory (RAM) units communicatively coupled to and associated with the plurality of processors in one-to-one correspondence; and
the one of the plurality of processors capable of transferring the update agent from the corresponding NAND memory unit into the corresponding RAM memory unit and of executing the update agent in the corresponding RAM memory unit to update the code to the mobile electronic device using less than full page NAND write blocks in order to be consistent with NOR memory unit updates to mobile electronic devices and to accommodate non-direct access to the plurality of NAND memory units and to accommodate bad blocks within the plurality of NAND memory units.
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Abstract
A network with mobile devices supports update of firmware and/or software from one version to another version, the firmware or software being stored in non-volatile memory of the mobile handset, such as a NAND flash memory. In one embodiment, a firmware stored in the NAND non-volatile memory is updated by an update agent in a fault tolerant mode.
145 Citations
22 Claims
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1. A mobile electronic device having a plurality of processors, each processor having its own address space, the mobile electronic device comprising:
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a plurality of NAND memory units communicatively coupled to and associated with the plurality of processors in one-to-one correspondence; an update agent executable on one of the plurality of processors, the update agent capable of updating code in the NAND memory unit corresponding to the one of the plurality of processors; an update package resident in the NAND memory unit corresponding to the one of the plurality of processors; the update agent employing the update package to update the code; a plurality of random access memory (RAM) units communicatively coupled to and associated with the plurality of processors in one-to-one correspondence; and the one of the plurality of processors capable of transferring the update agent from the corresponding NAND memory unit into the corresponding RAM memory unit and of executing the update agent in the corresponding RAM memory unit to update the code to the mobile electronic device using less than full page NAND write blocks in order to be consistent with NOR memory unit updates to mobile electronic devices and to accommodate non-direct access to the plurality of NAND memory units and to accommodate bad blocks within the plurality of NAND memory units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A mobile electronic device having a first processor and a second processor each having its own address space, the mobile electronic device comprising:
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a first NAND memory unit associated with and communicatively coupled to the first processor; a second NAND memory unit associated with and communicatively coupled to the second processor; each of the first processor and the second processor having an associated update agent capable of updating code; the first NAND memory unit and the second NAND memory unit each comprising a boot loader, an operating system (OS) image, and a user data section; a first update package resident in the first NAND memory unit of the first processor for use by the update agent of the first processor; the update agent for the second processor is resident in the first NAND memory unit of the first processor; the second processor is associated with and communicatively coupled to a random access memory (RAM) memory unit; and the update agent for the second processor is transferred from the first NAND memory unit of the first processor to the RAM memory unit for execution by the second processor to update the code to the mobile electronic device using less than full page NAND write blocks in order to be consistent with NOR memory unit updates to mobile electronic devices and to accommodate non-direct access to the first NAND memory unit and the second NAND memory unit and to accommodate bad blocks within the first NAND memory unit and the second NAND memory unit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification