Light emitting device methods

• US 7,799,585 B2
• Filed: 11/17/2008
• Issued: 09/21/2010
• Est. Priority Date: 04/15/2003
• Status: Expired due to Fees

• Current Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Original Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Inventors: Graff, John W., Minsky, Milan S., Erchak, Alexei A., Brown, Michael Gregory, Duncan, Scott W.
• Primary Examiner(s): Wilczewski; Mary
• Application Number:
  US12/272,120
• Publication Number:
  US 20090137072A1
• Time in Patent Office: 673 Days
• Field of Search: 438/22, 438/24, 438/25, 438/26, 438/29, 438/34, 438/46, 257/79, 257/98, 257/100, 257/103, 257/E21.52, 257/E33.025, 257/E33.028, 257/E33.033, 257/E33.034, 257/E33.056
• US Class Current: 438/26
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate

Abstract

Light-emitting device methods are disclosed.

Claims

1. A method of making a light emitting device, the method comprising:

providing a first multi-layer stack, comprising;

a substrate;

a submount, and

a semiconductor layer between the substrate and the submount, the semiconductor layer being supported by the submount wherein the semiconductor layer and submount are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the semiconductor layer by less than about 15%;

removing, at least partially, the semiconductor layer; and

removing the substrate from the first multi-layer stack to form a second multi-layer stack.

2. The method of claim 1, wherein the thermal expansion of the submount differs from the coefficient of thermal expansion of the semiconductor layer by less than about 10%.

3. The method of claim 1, wherein the coefficient of thermal expansion of the submount differs from the coefficient of thermal expansion of the semiconductor layer by less than about 5%.

4. The method of claim 1, wherein a thickness of the submount is greater than a thickness of the substrate.

5. The method of claim 1, wherein the submount is at least about 10 microns thick.

6. The method of claim 1, wherein the submount is at most about five millimeters thick.

7. The method of claim 1, wherein the substrate is at most about one millimeter thick.

8. The method of claim 1, wherein the submount has a cross-sectional area of at least about four inches.

9. The method of claim 1, wherein the semiconductor layer comprises a III-V semiconductor layer.

10. The method of claim 9, wherein the III-V semiconductor layer comprises a nitride.

11. The method of claim 9, wherein the III-V semiconductor layer comprises a gallium nitride compound.

12. The method of claim 1, wherein the submount comprises a material selected from the group consisting of germanium, silicon, silicon-carbide, copper, copper-tungsten, diamond, nickel-cobalt, and combinations thereof.

13. The method of claim 12, wherein the submount is copper-tungsten.

14. The method of claim 1, wherein the multi-layer stack includes a quantum well-containing region.

15. The method of claim 1, wherein the semiconductor layer is a buffer layer.

16. The method of claim 1, wherein removing the semiconductor layer exposes a surface of an n-doped semiconductor layer.

17. The method of claim 1, wherein removing the substrate from the first multi-layer stack results in formation of a residue on a surface of the buffer layer.

18. The method of claim 16, further comprising forming a dielectric function that varies spatially according to a pattern in the exposed surface of the n-doped semiconductor layer.

19. The method of claim 16, further comprising roughening the exposed surface of the n-doped semiconductor layer.

20. The method of claim 1, wherein the second multi-layer stack includes a bonding layer comprising a gold-tin alloy.