Method and apparatus for controlling charge transfer in CMOS sensors with a transfer gate work function

  • US 7,800,145 B2
  • Filed: 12/30/2004
  • Issued: 09/21/2010
  • Est. Priority Date: 12/30/2004
  • Status: Active Grant
First Claim
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1. An image sensor integrated circuit, comprising:

  • a plurality of photodetectors generating electrons excited by incident photons;

    a plurality of nodes, wherein each of the plurality of photo detectors has a corresponding node of the plurality of nodes;

    a plurality of transfer devices controlling a transfer of the electrons from said each of the plurality of photodetectors to the corresponding node, each of the plurality of transfer devices including;

    a first terminal coupled to one of the plurality of photodetectors;

    a second terminal coupled to one of the plurality of nodes; and

    a body between the first terminal and the second terminal; and

    a control terminal electrically coupled to the body, wherein the transfer of the electrons occurs through the body between the first terminal and the second terminal in response to a control voltage of sufficient value applied to the control terminal, and in an absence of the control voltage the control terminal creates an electric field tending to repel the electrons from a portion of the body by the control terminal;

    a plurality of p-type regions having a concentration stronger than a background p-type concentration of the plurality of transfer devices, wherein each of the plurality of p-type regions has a lateral position only partly under the control terminal of a transfer device of the plurality of transfer devices, the plurality of p-type regions controlling the transfer of electrons from a photodetector of the plurality of photodetectors to the corresponding node of the photodetector, and the plurality of p-type regions has the lateral position at least partly under the corresponding node, and the plurality of p-type regions has the lateral position stopping short of the plurality of photodetectors and stopping short of a plurality of reset devices;

    the plurality of reset devices, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active;

    row and column circuitry; and

    a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.

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